Clock ICs drive low-jitter Ethernet and PCIe
The SKY63104/5/6 family of jitter-attenuating clocks and the SKY62101 clock generator simultaneously generate ultra-low jitter clocks for synchronous Ethernet and spread-spectrum PCIe. Built on Skyworks’ fifth-generation DSPLL and MultiSynth technologies, these devices support flexible input-to-output frequency mapping and enable single-IC clock tree designs for demanding networking, data center, and industrial applications.
Typical DSPLL RMS jitter is as low as 18 fs (12 kHz–20 MHz at 625 MHz), with total output jitter around 55 fs RMS—well suited for 224G PAM4 Ethernet SerDes. The devices also meet spread spectrum clocking requirements for PCIe Gen 1 through Gen 6.
The jitter attenuators and clock generator provide 12 outputs in a compact 8×8-mm QFN package with wettable flanks. The SKY63104 includes one DSPLL with two MultiSynths; the SKY63105 has two DSPLLs and one MultiSynth; and the SKY63106 features three DSPLLs with no MultiSynth. Output frequencies span 8 kHz to 3.2 GHz, with configurable formats including LVDS, HCSL, LVPECL, LVCMOS, S-LVDS, and CML. Output-to-output skew is tightly controlled at ±50 ps, with per-output delay adjustable in 50-ps steps.
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