A 4-step guide to selecting PFC conduction mode: CrM/DCM vs. CCM

The power factor correction (PFC) boost converter is the industry-standard topology for meeting harmonic current regulations such as IEC 61000-3-2. This circuit is essential in modern AC/DC power supplies, where it shapes the input current (I_IN) to follow the input voltage (V_IN) sinusoidal waveform, achieving a power factor near unity.

The key to successful PFC design lies in its operating mode. While three basic modes exist—continuous conduction mode (CCM), discontinuous conduction mode (DCM), and critical conduction mode (CrM)—the fundamental design choice is between a system built for CCM and a system optimized for CrM. A controller designed for CrM naturally operates in DCM at lighter loads, meaning CrM and DCM are often analyzed together as a single design path (CrM/DCM).

Selecting between CCM and CrM/DCM presents a fundamental trade-off that directly impacts the converter’s efficiency, physical size, cost, and EMI performance.

Figure 1 shows the typical PFC boost converter schematic.

Figure 1 A typical PFC boost converter schematic shows the industry-standard topology for modern AC/DC power supplies. Source: MPS

Below is the 4-step guide to selecting PFC conduction mode. It provides a clear methodology for navigating the tradeoffs, beginning with the primary design constraint and culminating in an informed topology selection. 

Step 1: Identify primary design constraint

Before analyzing technical specs, the primary design constraint must be defined, as this informs the rest of the decision-making process. Common design constraints include:

• Maximum power density: Make the power supply as small and compact as possible.
• Minimum cost: Reducing the BOM is usually the most critical design factor.
• Maximum efficiency: Target a specific efficiency rating, for example, 80 PLUS Titanium, where every fraction of a percentage point matters.
• EMI performance: The product is intended for a sensitive environment, for example, medical, avionics, or high-fidelity audio, where passing strict EMI regulations is a major challenge.

Once the primary design constraint is identified, the next step is to analyze core trade-offs.

Step 2: Analyze core trade-offs of selected power range

While the ideal conduction mode is heavily dependent on the application’s power range, it’s crucial to first understand the inductor current (I_L) behavior in each mode, as this determines all other performance characteristics.

Figure 2 shows the fundamental difference between the I_L waveforms of the PFC boost modes (CCM and CrM) across a few switching cycles around the peak of the line half-cycle, where the average inductor current (I_{L_AVG}) is highest.

Figure 2 Note the fundamental differences between the I_L waveforms of the PFC boost modes. Source: MPS

The I_L behaviors in CCM and CrM are described below:

• CCM: I_L always remains above 0 A and has a relatively small triangular ripple current superimposed onto a large average inductor current (I_{L_AVG}).
• CrM: I_L is a series of triangles, where each cycle begins at 0 A. The current ramps up to a peak, then ramps back down to 0 A, at which point the next cycle immediately begins.

For selecting component stress and size, the peak switching current (I_{SW_PK}), required inductance (L_PFC), and dominant power losses must be calculated. These calculations are typically evaluated at the peak of the low-line AC input voltage (for example, 85 V_AC), which represents the worst-case scenario for the RMS inductor current (I_{L_RMS}) and peak inductor current (I_{L_PEAK}).

Peak Switching current

I_{SW_PK} determines the required current rating of the MOSFET and diode. The baseline for comparison is the average input current at the sinusoid peak (I_{IN_PK_AVG}).

The CCM peak switching current (I_{SW_PK_CCM}) can be calculated with Equation (1):

Where I_{IN_AVG} is the average input current, and K_R is the ripple factor (typically between 0.2 and 0.4).

The CrM peak switching current (I_{SW_PK_CRM}) can be calculated with Equation (2):

The peak current flowing through the switch and diode in CrM is about twice the peak current in CCM for the same input power (P_IN). This directly impacts conduction loss (I²R).

Required inductance

L_PFC determines the main magnetic component size. The required CCM inductance (L_{PFC_CCM}) can be calculated with Equation (3):

Where D_PK is the duty cycle at the peak input voltage (V_{IN_PK}), and f_SW is the switching frequency.

The required CrM inductance (L_{PFC_CRM}) can be calculated with Equation (4):

The required boost inductance depends strongly on the target ripple current and f_SW strategy. In many practical PFC designs, CCM uses a higher inductance to limit current ripple, while CrM can use a lower inductance at the expense of higher peak and RMS current.

Dominant power losses

Efficiency requires a trade-off between conduction loss and switching loss. Table 1 shows the dominant power losses in CCM compared to CrM/DCM.

Table 1 Here is a comparison of dominant power losses in CCM vs. CrM/DCM. Source: MPS

Based on Table 1, CCM reduces conduction loss with the disadvantage of high switching loss, meanwhile CrM eliminates the worst switching losses with the disadvantage of higher conduction loss. This understanding can be applied to different power ranges.

For low-power applications below 200 W, CrM/DCM is preferred. The high switching loss in CCM (from I_RR) is the dominant factor for power loss, which is eliminated in CrM. This leads to higher overall efficiency. For high-power applications exceeding 400 W, CCM is preferred. The total current is high enough to result in massive conduction losses from the I_RMS² penalty in CrM. These I_RMS² x R_DS(ON) losses far outweigh the advantages of lower switching loss, meaning CCM is more efficient overall.

Step 3: Verification using design decision map

A visual decision map can be used for verification by plotting the output power (P_OUT) against typical switching frequencies (see Figure 3).

Figure 3 A PFC mode design decision map (CrM/DCM vs. CCM) can be used for verification. Source: MPS

The ideal operating regions for each mode are described below:

• CrM/DCM recommended (green region in Figure 3): As established in step 2, when analyzing the core trade-offs, this region is ideal for CrM due to superior efficiency at light loads and lower cost.
• CCM recommended (red region in Figure 3): The lower conduction losses and smaller inductor size in CCM are ideal for high-power, high-density designs. Moreover, CCM offers advantages for conducted EMI and EMI filter designs due to its lower inductor current ripple and higher continuous input current.
• Transition zone (yellow region in Figure 3): The decision between selecting CrM/DCM and CCM depends on the primary design constraint identified in step 1.

Step 4: Select controller and explore alternatives

If a CrM/DCM controller is selected based on step 3, the design typically benefits from lower cost, good light-load efficiency, and reduced reverse-recovery-related switching stress.

If a CCM controller is selected based on step 3, using a fast-recovery or silicon carbide (SiC) boost diode can significantly reduce reverse-recovery-related losses and ease thermal design.

When selecting between a CrM/DCM and CCM controller, interleaved PFC architecture provides an alternative design that achieves higher performance, low switching loss, and EMI benefits. Interleaved PFC architecture can significantly reduce input current ripple and RMS current in both the input and output capacitors. This improves thermal stress and can reduce filtering requirements while preserving many of the switching loss advantages associated with transition mode.

Final design checklist

By following this 4-step guide to selecting PFC conduction mode, the correct topology can be selected according to the design specifications. A final checklist is provided below, summarizing the rules of thumb to keep in mind.

1. If the power is below 200 W, select CrM/DCM.
2. If the power exceeds 400 W, select CCM (with a SiC diode).
3. If the power is between 200 W and 400 W, select the PFC conduction mode based on the primary design constraints defined in step 1:

• Cost or EMI: CrM/DCM
• Size: CCM
• Performance: Interleaved CrM

Final design

Designing the CrM/DCM PFC stage is based on the calculation of the boost inductance and the peak stress on key switching components. Table 2 shows the design results.

Table 2 These design results are based on the calculation of boost inductance and peak stress on key switching components. Source: MPS

Take the case of the MP44018A chip employed for the PFC stage as a multi-mode controller operating in CrM and DCM via the ZCD pin (Figure 4). It’s designed to provide high-performance active PFC with a minimal number of external components. This PFC controller’s very low supply current achieves low standby power loss, with a typical no-load power consumption below 30 mW.

Figure 4 Here is how CrM/DCM PFC boost works using the MP44018A controller. Source: MPS

Light-load efficiency is improved through dead-time extension technology, which reduces the switching frequency under such conditions. Furthermore, MP44018A achieves lower total harmonic distortion (THD) compared to conventional constant-on-time (COT) control by utilizing a variable-on-time control strategy while in DCM.

Figure 5 shows the measured input current harmonic spectrum at V_IN = 230 V_AC and P_OUT = 240 W in a compliance-oriented view of boost PFC performance. The red bars correspond to the harmonic content achieved by the implemented PFC solution with MP44018A. The blue bars show the applicable IEC 61000-3-2 harmonic current limits for the target equipment class.

Figure 5 The harmonics results are compared to IEC 1000-3-2 Class C compatibility standard. Source: MPS

A strategic approach to conduction mode selection

Implementing an active PFC front-end is a critical requirement for modern AC/DC power supplies to ensure high efficiency and compliance with harmonic current regulations. This article demonstrated that selecting the proper conduction mode is foundational for PFC construction, directly impacting the converter’s efficiency, physical size, cost, and EMI performance.

A strategic approach to conduction mode selection helps optimize the final design to meet its specific application targets, whether that is maximum power density, minimum cost, or peak efficiency. For designs that follow the CrM/DCM path, a multi-mode controller can provide an effective solution for achieving strong light-load efficiency and harmonic performance with a low external component count.

A PFC front-end with a stable DC bus provides an ideal foundation for a high-efficiency secondary stage. Pairing this PFC front-end with a resonant LLC converter is a particularly effective strategy, enabling high-performance and high-density power solutions for markets ranging from consumer adapters to industrial supplies.

Rafael Collado is a supervisor at Monolithic Power Systems (MPS).

Related Content

• Design interleaving PFC boost power stages
• How to design a digital-controlled PFC, Part 1
• How to design a digital-controlled PFC, Part 2
• How to design a digital-controlled PFC, Part 3
• How to design a digital-controlled PFC, Part 4

The post A 4-step guide to selecting PFC conduction mode: CrM/DCM vs. CCM appeared first on EDN.