After TSMC fab in Japan, advanced packaging facility is next
Japan’s efforts to reboot its chip industry are likely to get another boost: an advanced packaging facility set up by TSMC. That seems a logical expansion to TSMC’s $7 billion front-end chip manufacturing fab built in Kumamoto on Japan’s…
AI boom and the politics of HBM memory chips
The high-bandwidth memory (HBM) landscape, steadily growing in importance for its critical pairing with artificial intelligence (AI) processors, is ready to move to its next manifestation, HBM3e, increasing data transfer rate and peak memory…
Alphawave demos 3-nm UCIe subsystem at 24 Gbps
Alphawave Semi announced the successful bring-up of its first chiplet-connectivity silicon platform on TSMC’s advanced 3-nm process. The silicon-proven Universal Chiplet Interconnect Express (UCIe) subsystem, capable of operating at 24 Gbps…
Edge AI/ML models team with Arm Keil MDK
Embedded developers can deploy AI and ML models developed on Edge Impulse’s platform directly in Arm’s Keil microcontroller development kit (MDK). The partnership between the two companies makes it easier for engineers to collaborate with…
Retimers boost PCIe 6.x connectivity
Astera Labs has expanded its Aries PCIe/CXL Smart DSP retimer portfolio with devices that ensure robust PCIe 6.x and CXL 3.x connectivity. Doubling bandwidth to 64 GT/s per lane with automatic link equalization, Aries 6 retimers enable critical…
Rad-tolerant LNA spans 2 GHz to 5 GHz
An off-the-shelf S-Band low-noise amplifier, the TDLNA2050SEP from Teledyne, tolerates up to 100 krads of total ionizing dose (TID) radiation. This makes the part suitable for use in high-reliability satellite communication systems and phase-array…
Scalable MCUs tout MPU-like performance
Outfitted with an Arm Cortex-7 core running at up to 600 MHz, ST’s STM32H7R/S MCUs provide the performance, scalability, and security of a microprocessor. They embed 64 kbytes of bootflash and 620 kbytes of SRAM on-chip to speed execution,…
Cache coherent interconnect IP pre-validated for Armv9 processors
Modern system-on-chip (SoC) designs require multiple interconnects for optimal performance, and here, cache coherent and non-coherent interconnects work together. In fact, it’s imperative that SoCs have an efficient combination of cache-coherent…
Non-linear digital filters Uses cases and sample code
Most embedded engineers writing firmware have used some sort of digital filters to clean up data coming from various inputs such as ADCs, sensors with digital outputs, other processors, etc. Many times, the filters used are moving average (boxcar),…
Non-linear digital filters Uses cases and sample code
Most embedded engineers writing firmware have used some sort of digital filters to clean up data coming from various inputs such as ADCs, sensors with digital outputs, other processors, etc. Many times, the filters used are moving average (boxcar),…
Power delivery for a load that is driven with multiple sources
When a load is driven simultaneously by more than one source with each source being of its own frequency, the individual load power deliveries from those sources are independent of each other. Whatever power any one of those sources would provide…
Power delivery for a load that is driven with multiple sources
When a load is driven simultaneously by more than one source with each source being of its own frequency, the individual load power deliveries from those sources are independent of each other. Whatever power any one of those sources would provide…
