Cache coherent interconnect IP pre-validated for Armv9 processors
Modern system-on-chip (SoC) designs require multiple interconnects for optimal performance, and here, cache coherent and non-coherent interconnects work together. In fact, it’s imperative that SoCs have an efficient combination of cache-coherent and non-coherent operations.
While SoC parts like accelerators and peripherals generally don’t require cache coherency, sharing a coherent view of memory and I/O is critical, so the processor has access to the most recent data without having to go off-chip. Arteris claims that its non-coherent FlexWay interconnect IP and Ncore cache coherent network-on-chip (NoC) IP seamlessly work together to offer SoC designers robust architectural flexibility.
The latest version of its cache-coherent NoC IP works with multiple processor IPs, including RISC-V and the next-generation Armv9 Cortex processor. Arteris has pre-validated Armv9 Cortex processor IP for its Ncore cache coherent interconnect IP, and the resulting validation system boots Linux on a multi-cluster Arm design and executes test suites to validate critical cache coherency cases.
It also supports multiple protocols, including CHI-E, with which the latest Armv9 processors are closely associated. Other protocols are CHI-B and ACE coherent, plus ACE-Lite and AXI* IO coherent interfaces. That allows chip designers to secure their investment in older architectures and evolve in a cost-effective manner.
Ncore can scale across a mix of fully coherent, I/O-coherent, non-coherent, memory and peripheral interfaces using a variety of NoC topologies. Source: Arteris
Next, Ncore cache coherent interconnect IP has achieved ISO 26262 certification from exida, a certification agency specializing in functional safety standards for the automotive industry. Previously, Arteris supported safety and designers would do their own hardware checking in terms of safety process. However, this Ncore version is certified, meaning that interconnect design is out-of-box ready with ISO 26262 certification.
On the software side, Ncore has a very logical user interface flow to accelerate design efficiency. The flow starts at the architectural level with chip specifications and system assembly configuration options. Then, it goes to the automatic mapping process of NoC library elements, followed by optimization and refinement before RTL is generated.
Moreover, compared to the manual approach, NCoR maintains a database of inputs that SoC architectures require. So, once the initial configuration is classified, which can be iterated, SoC designers can revisit each segment, making the job of managing SoC specifications a straightforward task.
Charles Janac, president and CEO of Arteris, says that SoC designers are challenged by the growing complexity resulting from the number of processing elements, multiple protocols, and functional safety requirements of modern electronics. “Our latest release of a production-proven Ncore marks an important milestone toward our ultimate cache coherent interconnect IP vision to connect any processor, using any protocol and topology.”
Ncore supports direct connections for heterogeneous, asymmetric systems and other flexible connectivity options, ensuring adaptability to various applications across automotive, industrial, communications, and enterprise computing markets. Arteris claims that Ncore can save SoC design teams upward of 50 years of engineering effort per project compared to manually generated interconnect solutions.
Related Content
Verifying Cache Coherence
Cache Coherence Issues for Real-Time Multiprocessing
SoC design: When is a network-on-chip (NoC) not enough?
SoC design: When a network-on-chip meets cache coherency
Efficient checks for cache-coherency verification in complex SoCs
googletag.cmd.push(function() { googletag.display(‘div-gpt-ad-native’); });
–>
The post Cache coherent interconnect IP pre-validated for Armv9 processors appeared first on EDN.
