FPGA IP accelerates deterministic networking
Orthogone’s Ultra-Low-Latency (ULL) FPGA IP Portfolio comprises production-ready networking and data-movement IP cores for AMD UltraScale+ and Versal adaptive platforms. The IP cores are designed for applications requiring determinism, low jitter, and reliability, with early adopters using them in aerospace, defense, and quantum computing applications.
The portfolio combines Ethernet MAC/PCS with optional Reed-Solomon FEC, hardware TCP/IP and UDP/IP offload engines, and a PCIe circular-buffer DMA controller for deterministic, sub-microsecond-class networking and packet processing. Offloading network processing to the FPGA reduces the packet-processing workload on the host CPU.
Ethernet MAC/PCS cores provide standards-compliant IEEE 802.3 Ethernet at 1G, 10G, 25G, 40G, and 100G line rates, with optional RS-FEC at 25G and 100G. TCP/IP and UDP/IP offload engines handle Layer 2 through Layer 4 processing in FPGA logic. The DMA controller enables bidirectional data movement between the host and FPGA over PCIe Gen3/Gen4.
The ULL FPGA IP Portfolio is available now for evaluation and licensing on AMD adaptive platforms.
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