Alphawave demos 3-nm UCIe subsystem at 24 Gbps
Alphawave Semi announced the successful bring-up of its first chiplet-connectivity silicon platform on TSMC’s advanced 3-nm process. The silicon-proven Universal Chiplet Interconnect Express (UCIe) subsystem, capable of operating at 24 Gbps per lane, was demonstrated at the recent Chiplet Summit in Santa Clara, CA.
Combining PHY IP and interface controller IP, the UCIe 1.1-compliant subsystem delivers high bandwidth density at very low power and with low latency. Its configurable die-to-die (D2D) controller supports streaming, PCIe/CXL, AXI-4, AXI-S, CXS, and CHI protocols. In addition, the PHY can be configured for TSMC’s chip-on-wafer-on-substrate (CoWoS) and integrated fanout (InFO) packaging technologies. Built-in bit error rate (BER) health monitoring ensures reliable operation.
“Achieving 3nm silicon-proven status for our 24-Gbps UCIe subsystem is a key milestone for Alphawave Semi, as it is an essential piece of our chiplet connectivity platform tailored for hyperscaler and data-infrastructure applications,” said Letizia Giuliano, VP IP Product Marketing at Alphawave Semi. “We are thankful to our TSMC team for their outstanding support, and we look forward to accelerating our mutual customers’ high-performance chiplet-based designs on TSMC’s leading-edge 3nm process.”
Read more about the UCIe subsystem on Alphawave Semi’s blog.
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