• Become a member
  • Log In
The Institution of Electronics
  • Home
  • About us
    • Our Objectives
    • Our History
    • Governance of the Institution
  • The Electron Magazine
    • 2024
      • 2024 – Winter
      • 2024 – Spring
      • 2024 – Summer
      • 2024 – Autumn
    • 2025
      • 2025 – Winter
      • 2025 – Spring
      • 2025 – Summer
      • 2025 – Autumn
    • 2026
      • 2026 – Winter
      • 2026 – Summer
  • Members
    • Membership Grades and Fees
    • Members’ Resources
      • The Electron Newsletter
      • The Archives
  • Education and Projects
    • National Electronics Competition
    • Student Members’ Projects
    • Arkwright Engineering Scholarships
  • News
  • Contact Us
  • Menu Menu
Uncategorised

Neural processor IP tackles generative AI workloads

Ceva has enhanced its NeuPro-M NPU IP family to bring the power of generative AI to infrastructure, industrial, automotive, consumer, and mobile markets. The redesigned NeuPro-M architecture and development tools support transformer networks, convolutional neural networks (CNNs), and other neural networks. NeuPro-M also integrates a vector processing unit to support any future neural network layer.

The power-efficient NeuPro-M NPU IP delivers peak performance of 350 tera operations per second per watt (TOPS/W) on a 3-nm process node. It is also capable of processing more than 1.5 million tokens per second per watt for transformer-based large language model (LLM) inferencing.

To enable scalability for diverse AI markets, NeuPro-M adds two new NPU cores: the NPM12 and NPM14 with two and four NeuPro-M engines, respectively. These two cores join the existing NPM11 and NPM18 with one and eight engines, respectively. Processing options range from 32 TOPS for a single-engine NPU core to 256 TOPS for an eight-engine NPU core.

NeuPro-M meets stringent safety and quality compliance standards, such as ISO 26262 ASIL-B and Automotive Spice. Development software for NeuPro-M includes the Ceva Deep Neural Network (CDNN) AI compiler, system architecture planner tool, and neural network training optimizer tool.

The NPM11 NPU IP is generally available now, while the NPM12, NPM14, and NPM18 are available to lead customers.

NeuPro-M product page

Ceva

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

<!–
googletag.cmd.push(function() { googletag.display(‘div-gpt-ad-native’); });
–>

The post Neural processor IP tackles generative AI workloads appeared first on EDN.

10 August 2023
http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 0 0 http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 2023-08-10 20:14:252023-08-10 20:14:25Neural processor IP tackles generative AI workloads

Latest news

  • Some tips for electrical engineers18 September 2026 - 13:08
  • FPGA architecture: SEU detection and recovery strategies18 September 2026 - 09:06
  • Highly integrated approach to power system design in the AI era17 September 2026 - 15:51
  • SFP: Add-in module delivers diminutive performance, flexibility17 September 2026 - 13:46
  • Pin-compatible MPUs simplify product variants17 September 2026 - 01:36
  • Anti-surge resistors reduce component count17 September 2026 - 01:36
  • SPAD sensor processes photon events on-chip17 September 2026 - 01:36
  • Transient voltage suppression devices reach 11 kW with flat clamping17 September 2026 - 01:36
  • Sensor sharpens infrared in-cabin imaging17 September 2026 - 01:36
  • FPGA architecture: Radiation particle types and single event upsets (SEUs)16 September 2026 - 14:25
IOE LOGO 2

Become a member

click here

Become a member

click here

Become a subscriber

click here

Become a sponsor

click here

© Copyright - The Institution of Electronics | Website by WHD Solutions
  • Link to LinkedIn
  • Link to Facebook
  • Link to X
Link to: Memory module promotes CXL 2.0 adoption Link to: Memory module promotes CXL 2.0 adoption Memory module promotes CXL 2.0 adoption Link to: Power ICs embed MCU and CAN FD interface Link to: Power ICs embed MCU and CAN FD interface Power ICs embed MCU and CAN FD interface
Scroll to top Scroll to top Scroll to top