• Become a member
  • Log In
The Institution of Electronics
  • Home
  • About us
    • Our Objectives
    • Our History
    • Governance of the Institution
  • The Electron Magazine
    • 2024
      • 2024 – Winter
      • 2024 – Spring
      • 2024 – Summer
      • 2024 – Autumn
    • 2025
      • 2025 – Winter
      • 2025 – Spring
      • 2025 – Summer
      • 2025 – Autumn
    • 2026
      • 2026 – Winter
  • Members
    • Membership Grades and Fees
    • Members’ Resources
      • The Electron Newsletter
      • The Archives
  • Education and Projects
    • National Electronics Competition
    • Student Members’ Projects
    • Arkwright Engineering Scholarships
  • News
  • Contact Us
  • Menu Menu
Uncategorised

Memory module promotes CXL 2.0 adoption

Micron is sampling its CZ120 memory expansion module, which features a PCIe 5.0 x8 interface and supports the Compute Express Link (CXL) 2.0 standard. The CXL Type 3 module provides storage capacities of 128 Gbytes and 256 Gbytes in an EDSFF E3.S 2T form factor.

With a dual-channel memory architecture and Micron’s high-volume production DRAM process, the CZ120 achieves higher module capacity and increased bandwidth. The device has a read/write bandwidth of up to 36 Gbytes/s (measured by running MLC workload with 2:1 read/write ratio on a single CZ120 memory expansion module).

“Micron is advancing the adoption of CXL memory with this CZ120 sampling milestone to key customers,” commented Siva Makineni, vice president of the Micron Advanced Memory Systems Group. “We have been developing and testing our CZ120 memory expansion modules utilizing both Intel and AMD platforms capable of supporting the CXL standard. Our product innovation coupled with our collaborative efforts with the CXL ecosystem will enable faster acceptance of this new standard, as we work collectively to meet the ever-growing demands of data centers and their memory-intensive workloads.”

Qualified customers and partners can enroll in Micron’s Technology Enablement Program (TEP) to gain early access to technical information and support to aid in the development of CXL-enabled memory expansion products.

CZ120 product page

Micron Technology 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

<!–
googletag.cmd.push(function() { googletag.display(‘div-gpt-ad-native’); });
–>

The post Memory module promotes CXL 2.0 adoption appeared first on EDN.

10 August 2023
http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 0 0 http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 2023-08-10 20:14:252023-08-10 20:14:25Memory module promotes CXL 2.0 adoption

Latest news

  • Bear on a power pole7 August 2026 - 13:46
  • Why software-defined systems require a dynamic data layer7 August 2026 - 10:42
  • Paper-based passives show impact of re-thinking substrate6 August 2026 - 16:22
  • Drone bans harm customers and don’t actually close the door6 August 2026 - 13:20
  • BMICs enable scalable battery monitoring6 August 2026 - 04:16
  • DDR5 MRDIMM chipset boosts server bandwidth6 August 2026 - 04:16
  • MCUs streamline single-motor control6 August 2026 - 04:16
  • MRDIMM enables higher DDR5 bandwidth6 August 2026 - 04:16
  • CXL controller scales server memory6 August 2026 - 04:16
  • Hz to 4-20mA or 0-20mA current source is compatible with grounded loads5 August 2026 - 13:57
IOE LOGO 2

Become a member

click here

Become a member

click here

Become a subscriber

click here

Become a sponsor

click here

© Copyright - The Institution of Electronics | Website by WHD Solutions
  • Link to LinkedIn
  • Link to Facebook
  • Link to X
Link to: Simulation in AI models revs up software-based auto designs Link to: Simulation in AI models revs up software-based auto designs Simulation in AI models revs up software-based auto designs Link to: Neural processor IP tackles generative AI workloads Link to: Neural processor IP tackles generative AI workloads Neural processor IP tackles generative AI workloads
Scroll to top Scroll to top Scroll to top