Marvell’s 2-nm silicon boosts AI infrastructure
Marvell Technology has demonstrated its first 2-nm silicon IP, enhancing the performance and efficiency of AI and cloud infrastructure. Built on TSMC’s 2-nm process, the working silicon is a key component of Marvell’s platform for developing next-generation custom AI accelerators, CPUs, and switches.
The company’s strategy focuses on developing a comprehensive semiconductor IP portfolio, including electrical and optical SerDes, die-to-die interconnects for 2D and 3D devices, advanced packaging technologies, silicon photonics, custom HBM compute architecture, on-chip SRAM, SoC fabrics, and compute fabric interfaces like PCIe Gen 7.
Additionally, the portfolio includes high-speed 3D I/O for vertically stacking die inside chiplets. This simultaneous bidirectional I/O operates at speeds up to 6.4 Gbps. By shifting from conventional unidirectional I/O to bidirectional I/O, designers can double the bandwidth and/or reduce the number of connections by 50%.
“Our longstanding collaboration with TSMC plays a pivotal role in helping Marvell develop complex silicon solutions with industry-leading performance, transistor density, and efficiency,” said Sandeep Bharathi, chief development officer at Marvell.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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