Keysight elevates chiplet design environment
Chiplet PHY Designer 2025 from Keysight offers simulation capabilities for UCIe 2.0 and support for the Open Compute Project Bunch of Wires (BoW) standard. Tailored to AI and data center applications, this digital chiplet design and die-to-die (D2D) platform enables pre-silicon level validation, streamlining the path to tapeout.
The Chiplet PHY Designer aids chiplet development by ensuring interoperability with UCIe 2.0 and BoW standards, enabling seamless integration within advanced packaging ecosystems. It accelerates time-to-market by automating simulation and compliance testing setup, including Voltage Transfer Function (VTF) analysis, simplifying design workflows.
Enhancing design accuracy, the toolset provides insight into signal integrity, bit error rate (BER), and crosstalk analysis, minimizing the risk of costly silicon re-spins. It also optimizes clocking designs by supporting advanced schemes like quarter-rate data rate (QDR), ensuring precise synchronization for high-speed interconnects.
To read about what’s new in Chiplet PHY Designer 2025, click here.
Chiplet PHY Designer product page
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