Analog in-memory computing advances to 12 nm
TetraMem has completed tapeout of the MLX300, a 12-nm analog in-memory computing (A-IMC) SoC based on multi-level RRAM technology. The chip was developed using Synopsys EDA software delivered through Synopsys Cloud FlexEDA, extending multi-level RRAM-based AI chip development to advanced FinFET nodes.
The MLX300 tapeout follows TetraMem’s MLX200/MLX200M multi-level RRAM A-IMC SoCs, which completed full-mask tapeout in 2026 on a commercial 22-nm process.
TetraMem’s architecture enables scalable AI accelerator development while improving performance per watt and reducing data movement. The MLX300 uses this architecture in a single-chip accelerator for audio, vision, and smaller language models. It supports up to 64 million INT4 parameters on-chip without external DRAM for model-weight storage. TetraMem says the SoC targets energy efficiency exceeding 50 TOPS/W.
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