Clustered-bit PWM DAC pedals and settles in a “unicycle”
This engineer combines a fellow contributor’s design and analysis data with his own to deliver a “bit” better circuit result.
In his recent Design Idea, “DAC implementations: The spread-bit PWM strikes back”, frequent and favored contributor Christopher Paul does a terrific analysis of “spread-bit” versus “clustered-bit” PWM DACs. Something in Christopher’s results that I found particularly super impressive (and surprising) was his detailed tabulation of settling times for spread-bit DACs (see his Table 1). When combined with his design methods for precision 3rd order unity-gain ripple filters, they provide peak-to-peak ripple amplitudes of Vpp = 1/N.
What’s especially nifty is that, when normalized for length of the PWM cycle time (2b / 1mHz clock) and tabulated for some popular resolutions from b = 8 to 16, the number of PWM cycles required for the output voltage to settle to within one least significant bit (LSB) does a very interesting thing. It hovers around only 2 to 3 cycles. That was an impressive result. But of course it made me wonder if there might be a way to do perhaps even a a bit better.
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So I started digging. I didn’t really expect to succeed. But I found a candidate—from the Design Ideas archives of nearly two decades ago. The circuit in Figure 1 of “Fast-settling synchronous-PWM-DAC filter has almost no ripple” (full disclosure: also written by yours truly) avoids most of the problems of low-pass filtering by combining a differential integrator, A1, with a sample-and-hold amplifier, A2, in a feedback loop operating synchronously with the PWM cycle, T2 in Figure 2 of that same article.
If you make the integrator time constant equal to the PWM cycle time—that is, R1C1 =T2 —and, if the sample capacitor, C2, equals the hold capacitor, C3, then the filter can acquire and settle to a new DAC value in exactly one PWM-cycle time, i.e., a “unicycle!” Ripple suppression of the synchronous filter is, in theory, infinite. The only practical limit (there’s at least one of those, isn’t there?) is nonzero-charge injection from S2 into C3. However, the choice of a low-injected-charge switch for S2 and appropriately generous capacitances for C2 and C3 can easily result in ripple amplitudes in the order of microvolts.
Rewind to the present.
Figure 1 below shows that legacy circuit updated and supplied with an integrator time constant settling-time trim (R1). This simple mod completely removes the requirement stated in the 2008 Design Idea that the single-cycle settling critically depends on C2 and C3 being precisely equal.
Figure 1 This “unicycle” DAC ripple filter combines a differential integrator, A1a, with a sample-and-hold amplifier, A1b, in a feedback loop operating synchronously with the PWM and sample-and-hold timing signals. Note that the integrator time constant shown is centered around 65.4ms and 16bit “clustered bit” PWM resolution.
You can just twiddle R1 to precisely achieve the single-PWM-cycle (unicycle) settling. Note that this single adjustment not only effectively compensates for and cancels out the C2 and C3 tolerance, but also accommodates all integrator feedback loop passive components (i.e., R2, C1, C2, and C3). The compensation even includes U1 internal switch Rons.
However neither R1 nor the passive component tolerances have any effect on Vout = PWMdutycycle x Vref conversion accuracy, which is inherent—apart from small effects due to op amp A1 non-idealities (mainly comprising finite DC gain and input offset) and single-digit-ohms U1 internal switch mismatch. The latter are minimized by the paralleling of the U1a and U1b sections shown in Figure 1.
If R1 is adjusted so that (R1 + R2)C1C3/C2 = Tpwm = 216 /1MHz, a precise unicycle settling will complete in exactly one 16-bit 65.536ms PWM cycle time (Figure 2). The final Vout = PWMdutycycle x Vref is inherent and is unaffected by R1 adjustment or passive part tolerances.
Figure 2 This settling DAC timing diagram sketch details the unicycle result.
It’s perhaps also worth noting that because rapid settling for this circuit doesn’t rely on “spread-bit” techniques with their dependence on software execution times, microcontrollers’ built-in PWM peripherals can be used for timing signal generation. This of course makes order-of-magnitude faster PWM frequencies and even faster settling times available. If required, that is.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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