Clock buffers pair low jitter with I/O flexibility
Operating from DC to 3.1 GHz, the SKY53510, SKY53580, and SKY53540 clock buffers from Skyworks provide 10, 8, and 4 outputs, respectively. These low-jitter devices support high-speed communication infrastructure, including data centers, 5G networks, and PCIe 7.0.
Each device integrates a 3:1 input multiplexer that accepts two universal inputs—compatible with LVPECL, LVDS, S-LVDS, HCSL, CML, SSTL, and HSTL—as well as a crystal input (also usable with a single-ended clock). The inputs support slew rates down to 0.75 V/ns. Differential outputs are arranged in two banks, with each bank independently selectable as LVPECL, LVDS, HCSL, or tristate and powered by its own 1.8-V, 2.5-V, or 3.3-V supply.
The buffers achieve low additive jitter, specified at 35 fs typical (47 fs max) at 156.25 MHz and 3 fs at 100 MHz for PCIe 7. Multiple on-chip LDO regulators provide >70 dBc PSRR in noisy environments, while a -166 dBc/Hz noise floor allows operation with Synchronous Ethernet (SyncE) at 156.25 MHz.
Samples and production quantities of the SKY53510/80/40 clock buffers are available now.
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