Automated IC layout tool integrated into foundry PDK
The Calibre DesignEnhancer software, which Siemens EDA unveiled at the Design Automation Conference (DAC) in July 2023, has been incorporated into a process design kit (PDK) of Samsung Foundry. The software provides multiple use models that perform automatic layout optimizations to improve power robustness and reduce design cycles during IC design implementation.
IC design engineers have traditionally relied on third-party place-and-route tools to incorporate design for manufacturing (DFM) optimizations. However, that often requires multiple time-consuming runs before converging on a “DRC-clean” solution.
Source: Siemens EDA
Calibre DesignEnhancer—which supports automated layout optimization during the IC design and implementation stages—helps IC designers deliver “DRC-clean” designs to tape out faster while improving design manufacturability and circuit reliability. Here, its via insertion use-model automatically inserts additional Calibre nmDRC-correct vias into layouts to reduce resistance that can minimize both voltage (IR) drop and electrostatic discharge (ESD) events in IC designs.
Siemens EDA claims that its layout tool enables design teams to significantly shorten turnaround time and reduce EM/IR issues while preparing a layout for physical verification. Calibre DesignEnhancer optimizes IC designs by reducing or even eliminating IR drop and electromigration (EM) issues quickly and accurately.
It does that by automatically implementing ‘Calibre correct-by-construction’ design layout modifications much earlier in the IC design and verification process. Luigi Rolandi, senior director for R&D at STMicroelectronics, acknowledged that Calibre DesignEnhancer proved instrumental in addressing and resolving out of specification resistance and IR drop issues.
JoongWon Jeon, a distinguished engineer of foundry technology development team at Samsung Electronics, also recognized that Calibre DesignEnhancer has provided mutual customers a step function increase in via insertion efficiency. “That leads to faster turnaround time compared to classic approaches to the problem.” For instance, while traditional place-and-route processes often require design teams to conduct multiple runs, Calibre DesignEnhancer in Samsung PDK helps IC designers achieve substantial first-pass gains.
Calibre DesignEnhancer integrates with all major design and implementation environments using industry interface standards and comes with kits for all leading foundries, supporting designs from 130-nm to 2-nm process nodes.
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