RISC-V Summit spurs new round of automotive support
The adoption of RISC-V with open standards in automotive applications continues to accelerate, leveraging its flexibility and scalability, particularly benefiting the automotive industry’s shift to software-defined vehicles. Several RISC-V IP core and development tool providers recently announced advances and partnerships to drive RISC-V adoption in automotive applications.
In July 2025, the first Automotive RISC-V Ecosystem Summit, hosted by Infineon Technologies AG, was held in Munich. Infineon believes cars will change in the next five years more than in the last 50 years, and as traditional architectures come to their limit, RISC-V will be a game-changer, enabling the collaboration between software and hardware.
However, RISC-V adoption will require an ecosystem to deliver new technologies for the automotive industry. The summit showcased RISC-V solutions and technologies ready for automotive, particularly for SDVs, bringing together RISC-V players in areas such as compute IP, software, and development solutions.
Fast-forward to October with several RISC-V players expanding the enabling ecosystem for automotive with key collaborations ahead of the October 2025 RISC-V Summit. Quintauris, for example, announced several partnerships, including with Andes Technology Corp., Everspin Technologies, Tasking, and Lauterbach GmbH, all focused on advancing RISC-V for automotive and other safety-critical applications.
The Quintauris strategic partnership with Andes, a provider of RISC-V processor cores, brings Andes’s RISC-V processor IP into Quintauris’s RISC-V-based portfolio, consisting of profiles, reference architectures, and software components. The partnership will focus on automotive, industrial, and edge computing applications. It kicks off with the integration of the 32-bit ISO 26262–certified processor in the AndesCore processor series with Quintauris’s automotive real-time reference architecture.
Quintauris is also teaming up with Everspin to bring its advanced memory solutions—magnetoresistive RAM technologies—into Quintauris’s reference architectures and real-time platforms for automotive, industrial, and edge applications. This partnership addresses the need for memory subsystems to meet the high standards for performance and functional safety in automotive applications.
In the development tools space, Quintauris announced a new partnership with Tasking to bolster RISC-V development in the automotive industry. Delivering certifiable development tools for safety-critical embedded software, Quintauris will integrate Tasking’s RISC‑V compiler into its upcoming RISC‑V reference platform.
Addressing embedded systems debugging, the new Quintauris and Lauterbach collaboration focuses on safety-critical industries such as automotive. Under the partnership, Lauterbach’s TRACE32 toolset, including a debug and trace suite, for embedded systems will be integrated into the Quintauris RISC-V reference platform. The TRACE32 toolset provides debugging, traceability, and system analysis tools.
Lauterbach also announced in October that its TRACE32 development tools support Tenstorrent’s system-on-chips (SoCs) and chiplets for RISC-V and AI-based workloads in the automotive, client, and server sectors. Tenstorrent’s automotive and robotics base die SoC targets automotive applications in SDVs. The SoC implements at least eight 64-bit superscalar, out-of-order TT-Ascalon RISC-V cores with vector and hypervisor ISA extensions, along with RISC-V-based AI accelerators and additional RISC-V cores for system and communication management.
The TRACE32 development tools allow simultaneous debugging of the TT-Ascalon RISC-V processors and other cores implemented on the chip, from pre-silicon development to prototyping on silicon and in-field debugging on electronic control units.
Also helping to accelerate the global adoption of RISC-V, Tenstorrent and CoreLab Technology are collaborating on an open-architecture computing platform for automotive edge and robotics applications. The Atlantis computing platform addresses demanding AI computing requirements, delivering a scalable, safety-ready CPU IP portfolio. The platform will leverage Tenstorrent’s RISC-V CPU IP and CoreLab Technology’s energy-efficient IP and SoC solutions.
Designed to deliver on performance, power efficiency, low total cost of ownership, and customization, all RISC-V CPU cores in the platform support deep customization, enabling customers to tailor their compute resources for their applications, according to Tenstorrent.
The automotive industry demands that ecosystem players meet stringent functional safety and security standards. To meet these requirements, Codasip recently announced that two of its high-performance embedded processor cores, the Codasip L735 and Codasip L739, have received TÜV SÜD certification for functional safety.
The L735 is certified up to ASIL-B and the L739 is certified up to ASIL-D, defined by the ISO 26262 standard. Both products are also compliant with ISO/SAE 21434 for cybersecurity in automotive development. In addition, Codasip’s IP development process is certified to both ISO 26262 and ISO/SAE 21434.
The L735 and L739 cores are part of the Codasip 700 family. The L735 includes safety mechanisms such as error-correcting code on caches and tightly coupled memories, a memory protection unit, and support for RISC-V RERI to provide standardized error reporting. The L739 adds dual-core lockstep, enabling ASIL-D certification.
Capability Hardware Enhanced RISC Instructions (CHERI) variants are available for both products. CHERI security technology protects against memory safety vulnerabilities. Codasip is standardizing a CHERI extension for RISC-V in collaboration with other members of the CHERI Alliance.
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