Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles

Editor’s Note: This is a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. The first part suggests mitigations and eliminations of common PWM error types. The second discloses circuits driven from various Vsupply voltages to power rail-rail op amps and enable their output swings to include ground and Vsupply. The third pursues the optimization of post-PWM analog filters. This fourth part pursues the optimization of post-PWM analog filters.

Part 1 can be found here.

Part 2 can be found here.

Part 3 can be found here.

Recently, there has been a spate of design ideas (DIs) published (see Related Content) which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, and limitations in accuracy. This is the fourth in a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations is implementable independently of the others. This DI addresses PWM sequence modifications which ease low pass analog filtering requirements.

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The tyranny of resolution vs response time

The combination of PWM clock frequency Fclk Hz and the number of bits b of PWM resolution dictates the lowest frequency (Fclk·2-b Hz) output component of a standard PWM. Over all the possible duty cycles, this component is also the largest and therefore the most challenging for an analog filter to suppress. For a given Fclk, the more bits of resolution, the longer the settling time will be of a filter which provides adequate suppression. But there is a way around this limitation.

Suppose a standard 8-bit PWM whose output is either 0 or 1 is configured for a duty cycle of (arbitrarily) 121/256. The first 121 states in a 256-state cycle would be 1 and the remaining 135 would be 0’s. But what if the first 128 states started with 60 ones and the last 128 states started with 61 ones? Let’s call this the “split-in-two” PWM. These two sequences have been offset in amplitude slightly so that they can be clearly seen on a graph shown in Figure 1.

Figure 1 Output sequences of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).

The blue waveform represents the standard PWM and the orange one is the split-in-two PWM. Why might the latter be advantageous? Consider the spectra of the two PWMs seen in Figure 2.

Figure 2 Frequency content of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).

The energy in the first harmonic of the split-in-two PWM is negligible in comparison with that of the standard PWM. The necessary attenuation for the first harmonic has been significantly lessened, and that which was required is now applied to the harmonic at double the frequency. A less aggressive attenuation-with-frequency analog filter can now be employed, resulting in a shorter settling time in response to a change in duty cycle.

Another way to look at this is to double the split-in-two PWM period to 512 states to produce a 9-bit PWM. As shown in Figure 3, the spectra of the two PWMs are almost identical because the time domain waveforms are almost identical—they differ only in that every other 256-bit sequence, one additional one-state replaces a zero-state. The higher resolution 9-bit PWM produces a small amount of energy (less than 1%) at half the frequency of the 8-bit’s fundamental. Any analog low pass filter with adequate suppression of the 8-bit fundamental frequency will more than sufficiently attenuate the signal at half that frequency.

Figure 3 Frequency content of a standard 8-bit PWM of duty cycle 121/256 and a split-in-two 9-bit PWM of duty cycle (121.5/256). They share the same clock, but the split-in-two’s period is twice the standard PWM’s.

The super-cycle

We can think of the split-in-two as generating a “super-cycle” consisting of two cycles of 2b states, each having at least S one-states, with 0 ≤ S < 2b. In one cycle, one zero-state could be swapped for a one-state if the total number of ones in the super-cycle is odd. This is a (b+1)-bit PWM with a period of 2b+1 states. But there is no reason to stop at two. There can be a super-cycle of 2n cycles where n is any integer. With each cycle capable of optionally swapping one zero-state for a one-state, this leads to a PWM super-cycle with a resolution of 2b+n bits. But unlike standard, non-super-cycle PWMs whose maximum spectral energy component is at fclk/2b+n Hz, the super-cycle’s is at a much higher fclk/2b Hz. As with the specific case of the split-in-two, this eases analog filtering requirements and results in a shorter settling time.

It’s worth thinking of a super-cycle as consisting of the sum of two different sequences. One is the S-sequence in which every cycle consists of an identical sequence of S contiguous one-states. The other is the X-sequence where each cycle optionally swaps the first zero-state following the last one-state with another one-state. The X-sequence has X one-states where 0 ≤ X < 2n. The duty cycle of the super-cycle is then (2n·S + X)/2b+n.

When n = 1 for a super-cycle, there is only one cycle where an extra one-state can reside. But when n > 1, X is also greater than one and the question becomes how to distribute the X ones among the 2n cycles so as to minimize the super-cycle’s energy at low frequencies. The fine folks at Microchip who manufacture the SAM D21 microcontroller not only have figured this out for us, but they have also implemented it in hardware [1]! For this IC, it is necessary only to write the values of X and S to separate registers to implement a super-cycle PWM; the hardware does the rest unsupervised. Fortunately, it is simple for almost any microprocessor to augment a standard PWM to implement a super-cycle. For each PWM cycle, the duty cycle count must be modified so that immediately after the sequence of S ones, the first zero gets changed to a one if and only if the following C expression is true for that cycle:

MASK & (cycleNbr * X) > MASK – X

Here, MASK = 2n– 1, X is as before, and cycleNbr is the numeric position of the cycle in the super-cycle. Figure 4 is a graph of the magnitudes of the lowest 32 harmonics of an n = 4, b = 8 super-cycle PWM. The graph provides evidence of the benefit of this approach.

Figure 4 First 32 harmonics of an n=4, b=8 super-cycle PWM. Spectra are displayed for X=1 through 8. (Spectra of X=9 through 15 are the same as those shown.)

The X-sequence’s energy is relatively low, having only 0 through 2n-1 one-states, but it also presents the lowest frequency component, fclk/2n+b Hz. The S-sequence generally contains the most energy by far (except for instances of very small duty cycles), but its smallest frequency component is noticeably higher at Fclk/2b Hz. Among the X sequences, X = 1 gives the largest amplitude for its first harmonic: 2-11 at fclk/2n+b Hz. The S sequence’s spectrum starts at the X sequence’s harmonic number 24 = 16 and produces its largest amplitude of 2/π for that harmonic when S = 211. If this were a standard PWM (an n = 0 super-cycle—no super-cycle at all that is, just a normal PWM), then that amplitude of 2/π would appear at frequency which is 16 times lower. The standard PWM presents a much more severe filtering problem. Its filter would take a lot longer to settle in response to a duty cycle change because of the much larger amount of low frequency attenuation required.

Comparing the filters for (n+b)-bit standard and super-cycle PWMs

The filtered AC steady state time-domain contributions of both the standard and the super-cycle (with its X and S sequences) PWMs should be less than some fraction α of the voltage of the PWMs’ one-state. A reasonable value of α is 2-(n+b+1), ½ LSB. This translates to an attenuation factor of 1/4 at the first harmonic of the X sequence. It is fortunate that even a simple two-component R-C filter meeting this requirement will sufficiently attenuate all higher X sequence harmonics, so there are no additional constraints to meet to suppress them. The 16th X harmonic frequency is that of the first S harmonic. Its PWM energy requires an attenuation factor of (π/2)·2-(n+b+1) at a 50% duty cycle. Again, any low pass filter meeting this requirement will adequately attenuate the remaining S-sequence harmonics. For an Fclk = 20 MHz, Figure 5 and Figure 6are graphs of the frequency and time domain step responses of 3rd order filters (two op-amps, 3 resistors, and 3 capacitors) meeting these requirements for standard 12-bit and super-cycle n = 4, b = 8 (12-bit) PWMs.

Figure 5 The frequency responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The maxima of the peaked waveforms are the maximum responses allowed for the filters at the peaked frequencies. The filters ensure that the steady state time domain energy at their outputs is less than ½ LSB of Full Scale.

Figure 6 The log of the absolute value of time responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The much shorter settling time of the super-cycle PWM is clearly evident.

Easing low pass analog filter requirements

When partnered with an appropriate analog filter, an approach to PWM embodiment available in hardware in an existing microprocessor [1] offers significantly shorter settling times than does a standard PWM. This approach can be implemented with the aid of a small amount of software in almost any microcontroller.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

References

https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21DA1-Family-Data-Sheet-DS40001882G.pdf(See section 31.6.3.3.)

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Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles

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