Nifty nulling of non-negligible dpot “scale” errors
This silly simple circuit cancels out potentially serious digital potentiometer zero- and full-scale errors.
Everybody (well, most everybody) knows that digipots tend to be more accurate when used as variable voltage dividers (i.e., in potentiometer mode) and not so much when used as variable resistors (in rheostat mode). In pot mode, many error-promoting effects like resistance element tolerances and temperature coefficients cancel out (well, mostly). But even when pots are used as actual pots, some small non-idealities might still sneak by. One (okay, two) of these are zero- and full-scale ratio errors.
Figure 1 shows a simple Dpot output buffer that should work fine when the error terms are small.
Figure 1 Dpot U1 runs in straightforward voltage-division potentiometer mode with unity-gain buffer A1 providing isolation from output loading. So everything should be nicely ideal with Vsigout = Vsigin(Rwa/Rba).
Unfortunately, sometimes the errors are not so small. For example, if U1 were an 8-bit (1/256) resolution MAX5451, then typical values for full-scale and zero-scale errors are listed in its datasheet as 8lsb = 3.1%, which makes the actual achieved accuracy look more like only 5 bits instead of the claimed 8.
Vsigout = Vsigin((Rwa/Rba)(1 – Fullscale) + (Rwb/Rba)(Zeroscale))
Fullscale = Zeroscale = 0.031 (typical)
Vsigout = Vsigin(Rwa/Rba) +/-3%
In any precision-critical application, those 3% offsets are likely to be unacceptable. Fortunately, Figure 2 suggests how a simple 3-resistor error-nulling fix is possible.
Figure 2 If R1 = R2 x (scale error) then the errors disappear and Vsigout = Vsigin(Rwa/Rba).
Here’s how it works. Note that, for best performance, R2 and R3 should equal each other to ~0.1% and R1 should be adjusted equal to R1 = ScaleErrorPercentage x R2. An easy way to accomplish this is as follows:
- Adjust U1 to its maximum UP setting. Then Rwa = Rba.
- Set SigIn = V+ – 100mV or so. The exact voltage isn’t critical; we’re just insuring that A1 won’t saturate.
- Connect a sensitive voltmeter between SigIn and SigOut.
- Adjust R1 to null the meter reading and force Vsigout = Vsigin.
Done.
In some applications, error cancellation might be good enough with R1 equal to a fixed value calculated from the datasheet figures, instead of needing post-assembly calibration. 31 kΩ, for example, would align with the MAX5451’s data.
Which might niftily null some non-negligible production costs.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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