• Become a member
  • Log In
The Institution of Electronics
  • Home
  • About us
    • Our Objectives
    • Our History
    • Governance of the Institution
  • The Electron Magazine
    • 2024
      • 2024 – Winter
      • 2024 – Spring
      • 2024 – Summer
      • 2024 – Autumn
    • 2025
      • 2025 – Winter
      • 2025 – Spring
      • 2025 – Summer
      • 2025 – Autumn
    • 2026
      • 2026 – Winter
      • 2026 – Spring
  • Members
    • Membership Grades and Fees
    • Members’ Resources
      • The Electron Newsletter
      • The Archives
  • Education and Projects
    • National Electronics Competition
    • Student Members’ Projects
    • Arkwright Engineering Scholarships
  • News
  • Contact Us
  • Menu Menu
Uncategorised

MRAM macro speeds read/write operations

Renesas presented an embedded MRAM macro in an MCU test chip at ISSCC 2024 that delivers a random-read access frequency of over 200 MHz. The test chip also exhibited a write throughput of 10.4-Mbytes/s.

The company developed two high-speed circuit technologies to achieve faster read and write operations in spin-transfer torque magnetoresistive RAM (STT-MRAM). A prototype MCU test chip, fabricated using a 22-nm process, combined the two technologies with a 10.8-Mbit MRAM memory cell array. Evaluation of the prototype chip confirmed the high-speed results at a maximum junction temperature of 125°C.

Advancements in read technology have enabled Renesas to achieve what it claims is the world’s fastest random read access time of 4.2 ns. Even taking into consideration the setup time of the interface circuit that receives the MRAM output data, the company was able to realize random read operation at frequencies in excess of 200 MHz. Further, improved write technology can improve MRAM write throughput 1.8-fold.

For greater detail, read the complete press release here.

Renesas Electronics 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

<!–
googletag.cmd.push(function() { googletag.display(‘div-gpt-ad-native’); });
–>

The post MRAM macro speeds read/write operations appeared first on EDN.

22 February 2024
http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 0 0 http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 2024-02-22 19:27:022024-02-22 19:27:02MRAM macro speeds read/write operations

Latest news

  • Secrets of Oscilloscope Time Measurements14 August 2026 - 13:44
  • Radon: Level detection, risk determination, and as-needed mitigation13 August 2026 - 13:16
  • TI a first mover in CAN XL transceivers13 August 2026 - 10:13
  • Four-channel USB-UART IC boosts server management13 August 2026 - 05:08
  • eFuse speeds overcurrent detection13 August 2026 - 05:08
  • Memory platform tackles AI bottlenecks13 August 2026 - 05:08
  • 6.5-kV SiC MOSFET reaches 8-kV blocking13 August 2026 - 05:08
  • Made by Google 2026: This limited silicon-supply situation really sucks13 August 2026 - 05:08
  • Cheap and cheerful LMC555 RC PWM pulse generator12 August 2026 - 13:56
  • Record high wafer shipments. Can fabs keep pace?12 August 2026 - 07:51
IOE LOGO 2

Become a member

click here

Become a member

click here

Become a subscriber

click here

Become a sponsor

click here

© Copyright - The Institution of Electronics | Website by WHD Solutions
  • Link to LinkedIn
  • Link to Facebook
  • Link to X
Link to: SP4T switches offer high isolation up to 8.5 GHz Link to: SP4T switches offer high isolation up to 8.5 GHz SP4T switches offer high isolation up to 8.5 GHz Link to: An MCU test chip embeds 10.8 Mbit STT-MRAM memory Link to: An MCU test chip embeds 10.8 Mbit STT-MRAM memory An MCU test chip embeds 10.8 Mbit STT-MRAM memory
Scroll to top Scroll to top Scroll to top