An MCU test chip embeds 10.8 Mbit STT-MRAM memory

A prototype MCU test chip with a 10.8 Mbit magnetoresistive random-access memory (MRAM) memory cell array—fabricated on a 22-nm embedded MRAM process—claims to accomplish a random read access frequency of over 200 MHz and a write throughput of 10.4 MB/s at a maximum junction temperature of 125°C.

Renesas, which developed circuit technologies for this embedded spin-transfer torque MRAM (STT-MRAM) test chip, presented details about it on February 20 at the International Solid-State Circuits Conference 2024 (ISSCC 2024) held on 18-22 February in San Francisco. The Japanese chipmaker has designed this embedded MRAM macro to bolster read access and write throughput for high-performance MCUs.

Figure 1 The MCU test chip incorporates a 10.8-Mbit embedded MRAM memory cell array. Source: Renesas

Microcontrollers in endpoint devices are expected to deliver higher performance than ever, especially in Internet of Things (IoT) and artificial intelligence (AI) applications. Here, the CPU clock frequencies of high-performance MCUs are in the hundreds of MHz, and to achieve greater performance, read speeds of embedded non-volatile memory need to be increased to minimize the gap between them and CPU clock frequencies.

However, MRAM has a smaller read margin than the flash memory used in conventional MCUs, which makes high-speed read operation more difficult. At the same time, MRAM is faster than flash memory for write performance because it requires no erase operation before performing write operations. That’s why shortening write times is desirable not only for everyday use but also for cost reduction of writing test patterns in test processes and writing control codes by end-product manufacturers.

Renesas has developed circuit technologies for an embedded STT-MRAM test chip with fast read and write operations to address this design conundrum.

Faster read and write

First, take MRAM reading, which is generally performed by a differential amplifier or sense amplifier to determine which of the memory cell current or reference current is larger. But because the difference in memory cell currents between the 0 and 1 states—read window—is smaller for MRAM than for flash memory, the reference current must be precisely positioned in the center of the read window for faster reading.

So, Renesas introduces two mechanisms to achieve faster read speed. First, it aligns the reference current in the center of the window according to the actual current distribution of the memory cells for each chip measured during the test process. Second, it reduces the offset of the sense amplifier.

Another challenge that Renesas engineers have overcome relates to conventional configurations, where large parasitic capacitance in the circuits is used to control the voltage of the bitline, so it doesn’t rise too high during read operations. While it slows the reading process, Renesas has introduced a Cascode connection scheme to reduce parasitic capacitance and speed up reading. That allows design engineers to realize the random read operation at more than 200 MHz frequencies.

Next, for write operation, it’s worth mentioning that Renesas announced in December 2021 that it has improved write throughput by applying write voltage simultaneously to all bits in a write unit using a relatively low write voltage generated from the external voltage (I/O power) of the MCU through a step-down circuit. Then, it used a higher write voltage only for the remaining few bits that could not be written.

Figure 2 In late 2021, Renesas announced an increase in the write speed of an STT-MRAM test chip manufactured on a 16-nm node.

Now, while power supply conditions used in test processes and by end-product manufacturers are stable, Renesas has relaxed the lower voltage limit of the external voltage. As a result, by setting the higher step-down voltage from the external voltage to be applied to all bits in the first phase, write throughput can be improved 1.8-fold. A faster write speed will contribute to more efficient code writing in endpoint devices.

Test chip evaluation

The prototype MCU test chip combines the above two enhancements to offer a 10.8 Mbit MRAM memory cell array fabricated using a 22-nm embedded process. The evaluation of the prototype chip validated that it achieved a random read access frequency of over 200 MHz and a write throughput of 10.4 MB/s.

The MCU test chip also contains 0.3 Mbit of one-time programmable (OTP) memory that uses MRAM cell breakdown to prevent falsification of data. That makes it capable of storing security information. However, writing to OTP requires a higher voltage than writing to MRAM, which makes it more difficult to perform writing in the field, where power supply voltages are often less stable. Here, Renesas suppressed parasitic resistance within the memory cell array, which in turn, makes writing in the field possible.

Renesas has vowed to further increase the capacity, speed, and power efficiency of MRAM.

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The post An MCU test chip embeds 10.8 Mbit STT-MRAM memory appeared first on EDN.

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