IP partnerships stir the world of FPGA chiplets
The tie-ups between IP suppliers of embedded FPGA (eFPGA) and UCIe chiplets mark a new era of FPGA chiplet integration in die-to-die connectivity. Chiplets are rapidly being adopted as heterogeneous multi-chip solutions to enable lower latency, higher bandwidth, and lower cost solutions than discrete devices connected via traditional interconnects on a PCB.
Take YorChip, a supplier of UCIe-compatible IP, which is employing QuickLogic’s eFPGA IP technology to create the first UCIe-compatible FPGA chiplet ecosystem. Unified Chiplet Interconnect Express (UCIe) is an open standard for connecting small, modular blocks of silicon called chiplets. Kash Johal, founder of YorChip, calls his company’s partnership with QuickLogic a giant leap for FPGA technology.
Figure 1 QuickLogic and YorChip have partnered to develop the industry’s first UCIe-enabled FPGA.
The two companies claim that this strategic partnership aims to enable an ecosystem allowing chiplet developers to create a customized system and use chiplets for prototyping and doing early market production. QuickLogic teamed up with connectivity IP supplier eTopus in a similar tie-up last year to create a disaggregated eFPGA-enabled chiplet template solution.
QuickLogic combined its Australis eFPGA IP Generator with chiplet interfaces from eTopus to produce standard eFPGA-enabled chiplet templates. Each template will be designed with native support for chiplet interfaces, including the bunch of wires (BOW) and UCIe standards. According to QuickLogic, unlike discrete FPGAs with pre-determined resources of FPGA lookup tables (LUTs), RAM, and I/Os, the disaggregated eFPGA-enabled chiplet template will be available initially as a configurable IP and eventually as known good die (KGD) chiplets.
Figure 2 The disaggregated eFPGA chiplet template solution supports both BOW and UCIe interfaces.
Such collaborations to create eFPGA–enabled chiplet solutions mark an important trend in developing chip-to-chip interconnect technology. In April 2023, the European research institute Fraunhofer IIS/EAS entered a collaboration with eFPGA IP supplier Achronix to build a heterogeneous chiplet solution.
Fraunhofer IIS/EAS, which provides system concepts, design services and fast prototyping in most advanced packaging technologies, will use Speedcore eFPGA IP from Achronix to explore chip-to-chip transaction layer interconnects such as BOW and UCIe. One key application in this project covers the connection of high-speed analog-to-digital converters (ADCs) alongside Achronix eFPGA IP for pre-processing in radars as well as wireless and optical communication.
Figure 3 Fraunhofer IIS/EAS has selected Achronix’s eFPGAs to build a heterogeneous chiplet demonstrator.
Brian Faith, CEO of QuickLogic says that these efforts to use eFPGA for building heterogeneous chiplets embody a new era of FPGA chiplet integration. And he sees their application in the evolving edge IoT and AI/ML markets. Nevertheless, the design journey toward building the world of FPGA chiplets has already started and we are likely to hear about more such partnerships incorporating FPGAs into chip-to-chip interconnect technology.
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