IP core provides scalable JESD204C connectivity
Achronix now offers a JESD204C IP core for connecting high-speed ADCs and DACs to programmable logic in Speedster7t FPGAs. Each core supports data rates of up to 32 Gbps per lane and up to eight lanes per link, delivering an aggregate serial line rate of up to 256 Gbps. Combining up to four cores enables aggregate performance of up to 1 Tbps.
Designed for high-bandwidth, multichannel data-converter systems, the standards-based JESD204C core maintains backward compatibility with JESD204B to ease legacy system migration. It supports both 64b/66b and 8b/10b encoding, along with Forward Error Correction (FEC), CRC-12, and CRC-3 modes. Subclass-1 operation provides deterministic, phase-coherent latency for single- and multichannel systems. Flexible framing, integrated alignment and recovery features, and an AXI-Lite interface simplify system integration and control.
Speedster7t FPGAs integrate 112-Gbps SerDes to achieve the signal integrity needed for 32-Gbps JESD204C links. A 2D network-on-chip (NoC) provides high-bandwidth data transport across the device while reducing programmable-routing congestion and power consumption.
The Achronix JESD204C IP core for Speedster7t FPGAs is available now. The IP package includes a graphical interface in the Achronix ACE design environment, synthesizable VHDL/Verilog design files, templates, and example designs.
The post IP core provides scalable JESD204C connectivity appeared first on EDN.
