Intel ups the advanced packaging ante with EMIB-T

Embedded Multi-die Interconnect Bridge-T (EMIB-T) was a prominent highlight of the Intel Foundry Direct Connect event. Intel is promoting this advanced packaging technology as a key building block for high-speed chiplet designs and has partnered with major EDA and IP houses to accelerate implementations around EMIB-T technology.

As the nomenclature shows, EMIB-T is built around the Embedded Multi-die Interconnect Bridge (EMIB) technology, a high-bandwidth, low-latency, and low-power interconnect for multi-die silicon. EMIB-T stands for EMIB-TSV and it supports high-bandwidth interfaces like HBM4 and Universal Chiplet Interconnect Express (UCIe). In other words, it’s an EMIB implementation that uses the through-silicon via (TSV) technique to send the signal through the bridge with TSVs instead of wrapping the signal around the bridge.

Figure 1 EMIB-T, which adds TSVs to the bridge, can ease the enablement of IP integration from other packaging designs. Source: Intel

Another way to see EMIB-T is the combination of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at die sizes beyond the reticle limit. Foveros is a 3D chip stacking technology that significantly reduces the size of bump pitches, increasing interconnect density.

All three major EDA powerhouses have joined the Intel Foundry Chiplet Alliance Program, which is intrinsically linked to EMIB-T technology. So, all three are working closely with Intel Foundry to develop advanced packaging workflows for EMIB-T. Start with Cadence’s solution, which helps streamline the integration of complex multi-chiplet architectures.

Next, Siemens EDA has announced the certification of a TSV-based reference workflow for EMIB-T. It supports detailed implementations and thermal analysis of the die, EMIB-T and package substrate, signal and power integrity analysis, and package assembly design kit (PADK)-driven verification.

Synopsys is also collaborating with Intel Foundry to develop an EDA workflow for EMIB-T advanced packaging technology using its 3DIC Compiler. In addition to the EDA trio, Intel Foundry has engaged other players for EMIB-T support. For instance, Keysight EDA is working closely with Intel Foundry to bolster the chiplet interoperability ecosystem.

Figure 2 The EMIB-T advanced packaging technology promises power, performance, and area (PPA) advantages for multi-die chiplet designs. Source: Intel

The EMIB-T silicon bridge technology is a major step toward harnessing advanced packaging for the rapidly emerging chiplets world. Intel Foundry Direct Connect highlighted how the Santa Clara, California-based chipmaker sees this advanced packaging technology in its future roadmaps. More technical details about EMIB-T are likely to emerge later in 2025.

Related Content

• Intel’s Embarrassment of Riches: Advanced Packaging
• EDA powerhouses align offerings with Intel’s 18A node
• Heterogeneous Integration Needs Tools, Business Models
• Intel bolsters EMIB packaging with EDA tools enablement
• Intel Foundry: We Are Listening and Learning from Our Customers

The post Intel ups the advanced packaging ante with EMIB-T appeared first on EDN.