Frequency divider from 1 to 4096 in increments of 1

Frequency dividers are usually realized on ICs and have a fixed and small division coefficient. In this article, a frequency divider is proposed that allows you to set the frequency division coefficient of a digital signal from 1 to 4096 in increments of 1.

Figure 1 shows the electrical circuit of the frequency divider. The input circuit contains a frequency multiplier made on two elements of the U1 CD4070 XOR chip. The doubled frequency signal enters the input of the pulse counter U2 CD4040 chip. This chip has 12 outputs, each of which is connected to one of the resistors R1–R12. The resistor matrix R1–R12 and its load resistance R14 form a voltage divider operating as follows. Each pulse entering the input of the frequency divider chip provides a step-by-step increase in voltage on the resistor R14. The capacitor C3 is designed to smooth out transients when switching the outputs of the U2 chip.

Figure 1 Frequency divider with stepwise switching of the division coefficient ranging from 1 to 4096 in increments of 1.

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The signal from the resistor R14 enters the comparison input (non-inverting input) of the comparator U3.1 LM339. The voltage from the potentiometer R13 is applied to the inverting input of the comparator. This voltage is compared with the voltage on resistor R14. When the voltage on the resistor R14 exceeds the voltage at the inverse input of the comparator, the comparator U3.1 will switch.

The signal from the comparator output goes to the counting input of the D-trigger on the U4.1 CD4013 chip. At the same time, the voltage from the comparator output is applied to the input R of the U2 CD4040 chip, zeroing the state of the counter. At the output of the trigger U4.1 CD4013, a rectangular signal with a fill factor D of 50% is formed. By adjusting the potentiometer R13, one can discretely change the division coefficient of the device from 1 to 4096 in increments of 1.

Figure 2 shows diagrams of signals observed at different points of the device. The upper row displays the signals received at the input of the U2 chip. The next row demonstrates a stepwise increase in voltage on the resistor R14 and, at the same time, switching the comparator when the voltage level set by potentiometer R13 is exceeded on the resistor R14. The next row demonstrates the signals generated when switching the comparator U3.1 at its output. And finally, the last row shows the type of signals generated at the output of the trigger U4.1 CD4013.

Figure 2 Diagrams of signals at different points of the frequency divider.

Since only one potentiometer R13 is used in Figure 1, it is difficult to set a given division coefficient. Figure 3 shows variants of the regulator. This is a fine adjustment using two potentiometers, as well as an ultra-fine adjustment using three potentiometers.

Figure 3 Execution options for the regulator of the comparison voltage setting.

If necessary, it is possible to lower the upper limit of the division coefficient by 2, 4, 8, etc. times by sequentially disconnecting the outputs Q12, Q11, Q10…of the U2 chip. Accordingly, the limiting division coefficient will decrease to 2048, 1024, 512, etc.

The maximum upper operating frequency of the device is 670 kHz. If necessary, this frequency can be increased by modifying the input frequency doubler made on the U1 CD4070 chip. The lower operating frequency has no limits.

Michael A. Shustov is a doctor of technical sciences, candidate of chemical sciences and the author of over 800 printed works in the field of electronics, chemistry, physics, geology, medicine, and history.

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Frequency divider from 1 to 4096 in increments of 1

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