Chiplets diary: Three anecdotes recount design progress

The chiplet design movement representing multi-billion-dollar market potential is marching ahead with key building blocks falling in place while being taped out at advanced process nodes like TSMC’s 3 nm. These multi-die packaging devices can now mix and match pre-built or customized compute, memory, and I/O ingredients in different process nodes, paving the way for system-in-packages (SiPs) to become the system motherboard of the future.

Chiplets also promise considerable cost reduction and improved yields compared to traditional system-on-chip (SoC) designs. Transparency Market Research forecasts the chiplet market to reach more than $47 billion by 2031, becoming one of the fastest-growing segments of the semiconductor industry at more than 40% CAGR from 2021 to 2031.

Below are a few anecdotes demonstrating how chiplet-enabled silicon platforms are making strides in areas such as packaging, memory bandwidth, and application-optimized IP subsystems.

Chiplets in standard packaging

While chiplet designs are generally associated with advanced packaging technologies, a new PHY solution claims to have used standard packaging to create a multi-die platform. Eliyan’s NuLink PHY facilitates a bandwidth of 64 Gbps/bump on a 3-nm process while utilizing standard organic/laminate packaging with 8-2-8 stack-up.

An efficient combination of compute density and memory bandwidth in a practical package construction will substantially improve performance-per-dollar and performance-per-watt. Moreover, chiplet-based systems in standard organic packages enable the creation of larger SiP solutions, leading to higher performance per power at considerably lower cost and system-level power.

Figure 1 Chiplets in standard packages could encourage their use in inference and gaming applications. Source: Eliyan

Eliyan has announced the tape-out of this die-to-die connectivity PHY at a 3-nm node, and the first silicon is expected in the third quarter of 2024. The tape-out includes a die-to-die PHY coupled with an adaptor layer/link layer controller IP to facilitate a complete solution.

Sub $1 chiplets

Chiplets have mostly been synonymous with high performance computing (HPC) applications, where these multi-die devices cost tens to hundreds of dollars. YorChip has joined hands with Siloxit to develop a data acquisition chiplet at a sub $1 price target in volume.

The two companies will leverage low-cost die-to-die links, physically unclonable function (PUF) security technology, and delta-sigma analog-to-digital (ADC) IP to create a cost-optimized chiplet. That’s how this chiplet aims to develop a low-cost die-to-die footprint that achieves 75% size savings over the competition.

High bandwidth memory (HBM) chiplets

Memory bandwidth is a major consideration alongside compute density and high-speed I/Os in chiplet designs. That makes high bandwidth memory 3 (HBM3) PHY a key ingredient in chiplets for applications such as generative AI and cloud computing. This is especially the case in HPC systems where memory bandwidth per watt is a key performance indicator.

Figure 2 The HBM3 memory subsystem supports data rates up to 8.4 Gbps per data pin and features 16 independent channels, each containing 64 bits for a total data width of 1,024 bits. Source: Alphawave Semi

Alphawave Semi has made available an HBM3 PHY IP that targets high-performance memory interfaces up to 8.6 Gbps and 16 channels. This HBM subsystem integrates the HBM PHY with a JEDEC-compliant, highly configurable HBM controller. It has been taped out at TSMC’s 3-nm node and is tailored for hyperscaler and data infrastructure designs.

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The post Chiplets diary: Three anecdotes recount design progress appeared first on EDN.

Chiplets diary: Three anecdotes recount design progress

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