Practical design for a multi-output flyback converter with improved cross-regulation

A stacked-output topology, combined with a weighted feedback network, improves cross-regulation in multi-output flyback converters. This approach allows the main regulated output and the stacked auxiliary output to contribute to the feedback loop, reducing the voltage deviation typically observed in semi-regulated flyback outputs.

This article applies that methodology to a complete offline auxiliary power supply based on a flyback controller. The design generates four output rails from an 85 V_AC to 265 V_AC input: a main regulated +5 V output, a stacked +12 V output, a post-regulated +3.3 V output, and a low-current -12 V auxiliary output.

The main design steps are presented, including the input bulk capacitor, transformer turns ratio, magnetizing inductance, current-sense resistor, weighted feedback network, and selection of the post-regulation stages.

The objective is not only to calculate the main power stage parameters, but also to show how the stacked-output topology and the weighted feedback network can be implemented in a practical converter. Experimental results are then used to evaluate the achieved cross-regulation, output voltage accuracy, and overall converter performance.

System architecture overview and design specifications

This section will present the complete system architecture designed to implement a stacked-output methodology. We’ll cover a high-level overview of the power stage partitioning and introduce the key ICs selected for each functional block.

Figure 1 shows the block diagram of the complete four-output power supply.

Figure 1 The above block diagram highlights the complete four-output flyback converter. Source: Monolithic Power Systems

The architecture is centered on a main flyback converter controlled by the MPX2002. This primary converter directly generates two positive rails (+5 V and +12 V) and a negative rail for the low-dropout (LDO) regulators. The final +3.3 V output is derived using a high-efficiency post-regulator. The specific roles and interactions are described below.

• Main regulated output (+5V): This is the primary regulated rail. The solution is based on the MPX2002, an all-in-one flyback controller with integrated 650-V primary control circuitry and a secondary 150-V synchronous rectification (SR) driver. Its key advantages are its integrated capacitive isolation, which replaces the traditional optocoupler, and quasi-resonant (QR) operation, which minimizes turn-on losses in the primary MOSFET.
• Stacked output (+12 V): This output is generated using the stacked topology, with its winding return path connected to the +5 V rail. Its regulation is achieved through the combination of passive tracking and active weighted feedback.
• Post-regulated output (+3.3 V): A high-efficiency synchronous buck converter steps down the regulated +12 V rail to +3.3 V. This approach is ideal for powering digital logic that requires a well-regulated voltage at a potentially high or dynamic current. The solution used in this example is the MP2332H, a fully integrated, high-frequency, synchronous buck converter.
• Low-current auxiliary output (-12 V): A dedicated winding from the flyback transformer feeds a simple LDO to generate the -12 V rail. This is a highly cost-effective solution to provide a stable negative voltage for low-power analog circuitry, such as operational amplifiers, where efficiency is not the primary concern. The suggested solution is based on the MP2015A, an LDO that can withstand a wide 2.5 V to 24 V input range.

Detailed design process

Step 1: Design inputs

Before starting the detailed design of the multi-output flyback converter, it’s essential to establish the core electrical specifications. These requirements dictate component selection, control strategy, and all subsequent calculations.

Table 1 Here is a summary of the design inputs. Source: Monolithic Power Systems

The following steps calculate the main parameters that make up the multi-output flyback converter.

Step 2: Flyback design

This section details the design of the core AC/DC flyback converter stage. The following key parameters will be explained and calculated:

• The required input bulk capacitance to maintain a stable DC bus voltage
• The turns ratio for each of the three secondary outputs, implementing the relationship from Equation (2)
• The transformer’s magnetizing inductance
• The primary current-sense (shunt) resistor
• The RMS currents that the primary and secondary power switches must withstand for proper dimensioning at a 90°C operating temperature

Step 2.1: Input bulk capacitor

The first design step addresses the input stage. Given the universal AC input range, which extends down to 85 V_AC, the converter requires a bulk capacitor to hold up the DC bus voltage. A common design guideline suggests a minimum capacitance of 1.5 µF per watt.

However, for this design, the high maximum ambient temperature of 90°C introduces a critical constraint. To avoid excessive primary root-mean square (RMS) current and the associated thermal stress at low-line conditions, the minimum DC voltage after the diode bridge (V_{BULK_MIN}) is explicitly limited to 85 V_DC.

Based on this specific voltage requirement, the bulk capacitance (C_BULK) can be calculated with Equation (1).

Since 59 µF is not a standard capacitance, the next higher standard value (62 µF/450 V) is selected. This choice provides additional hold-up margin.

Once the 62 µF input capacitance is selected, it’s crucial to calculate the maximum low-frequency input peak current (I_{IN_PEAK}) to properly size the EMI filter. This peak current is composed of two components: the current required to deliver power to the load (I_{LOAD_IN}) and the bulk capacitor’s peak charging current (I_{CBULK_PEAK}).

I_{LOAD_IN} is the average input current required by the converter at the minimum DC input voltage (85 V) and maximum output power (25 W). It can be estimated with Equation (2).

I_{CBULK_PEAK} is the transient peak that occurs at the moment the AC line voltage equals the minimum DC bus voltage. It can be calculated with Equation (3).

The total worst-case input peak current is the sum of these two components, providing a conservative design margin estimated with Equation (4).

Therefore, for the proper dimensioning of the input filter, the differential and/or common-mode choke must be designed to avoid saturation at this peak current of 1.99 A. This ensures that the harmonics generated by the converter under all line conditions are effectively filtered.

Step 2.2: Duty cycle and required turns ratio

Continuing with the flyback design, the MPX2002 controller supports both continuous conduction mode (CCM) and QR mode. Due to the wide input range, the converter operates in CCM at the minimum 85 V_AC input voltage.

Because the minimum DC input voltage is 85 V_DC and the +5V rail is the main regulated output, the maximum primary-to-secondary turn ratio (N_PS) can be calculated. This is done by enforcing a maximum duty cycle limit of 45% (D_MAX = 0.45) to prevent subharmonic oscillation. D_MAX can be calculated with Equation (5).

Where V_FWD is the worst-case voltage drop across the synchronous rectifier. Based on this limit, a standard integer turns ratio of N_PS1 = 12 is selected. This choice results in a maximum primary duty cycle of 41.62% at the minimum input voltage (V_IN).

Having selected the required turns ratio for the +5 V output and the maximum duty cycle, the required turns ratio for the stacked +12 V output can be estimated with Equation (6).

Where V_{FWD_D2} is the forward voltage drop of the +12 V output’s Schottky diode (0.6 V), and V_{FWD_Q2} is the voltage drop across the +5 V output’s synchronous rectification MOSFET (0.05 V).

According to the result, the turns ratio from the primary to the +12 V secondary (N_PS2) is a standard integer of 8.

According to the MP2015A’s datasheet, the negative output comes from a low-power linear regulator with a dropout of 0.7 V. The required turns ratio can be calculated with Equation (7).

Therefore, a primary to -12 V secondary turn ratio (N_PS4) of 4 (h = 0.25) is sufficient for operation.

Step 2.3: Peak current and magnetizing inductance

Once the duty cycle and turns ratio values required for the application have been obtained, it’s important to design the core of the converter: the transformer. The peak current values and its magnetizing inductance are essential for correct transformer sizing.

Therefore, considering a switching frequency (f_SW) of 70 kHz, the primary MOSFET turn-on time (t_ON) can be calculated using Equation (8).

To ensure CCM across the V_IN range and manage the inductor ripple, a current ripple factor (K_P) of 0.8 is selected. Given the average input current at low line (I_AV = 0.33 A, calculated with Equation 2), the peak primary current in standard CCM (I_PEAK) can be estimated with Equation (9).

Once I_PEAK is obtained, the magnitude of the current ripple (I_RIPPLE) can be estimated with Equation (10).

Finally, the required magnetizing inductance (L_M) can be calculated with Equation (11).

Thus, the primary transformer specifications are a magnetizing inductance of 479 µH, and a calculated maximum rated peak current of 1.32 A.

Step 2.4: Shunt resistor and ramp compensation

The voltage on the shunt resistor (V_SENSE) can be calculated with Equation (12).

Where V_{IPK_MAX} is the maximum peak voltage limitation in the current-sense pin, and S_RAMP is the internal slope compensation ramp. S_RAMP helps to damp the subharmonic oscillation due to CCM with a duty cycle close to 50%.

With V_SENSE, the shunt resistance (R_SENSE) can be calculated with Equation (13).

However, since subharmonic oscillations can occur, designers must check the stability of the converter by calculating the coefficient α with Equation (14).

Since coefficient α is much smaller than 1, this confirms that the converter will remain stable during CCM.

Step 2.5: Weighted feedback resistors

Once the converter’s most important parameters are calculated, designer must determine the maximum achievable regulation for the main outputs. First, the current (I₀) through the resistor from the feedback network (R₀) must be calculated, since it will determine the maximum allowed current through the resistor divider. I₀ can be calculated with Equation (15).

The weighted feedback resistances can be calculated to achieve 70% regulation for the +5 V output and 30% for the +12 V output using Equation (16) and Equation (17).

Thus, excellent cross-regulation can be achieved with weighted feedback and the stacked output structure.

Step 3: Linear regulator design

Once the flyback stage has been correctly designed, it’s important to calculate the main parameters that make up the linear regulator for the -12 V secondary output.

In this case, consider a value of 68 kΩ for the low-side feedback resistor (R₄), a trade-off between power loss and stability. The high-side resistance (R₃) can be estimated with Equation (18).

Step 4: Buck converter design

A key architectural decision involves the power source for the +3.3 V buck converter. Although the main regulated output is +5 V, a more strategic choice is to power the buck converter from the stacked +12 V rail. This configuration ensures that the buck converter’s own quiescent current provides a minimum load on the +12 V output. This small, constant load is critical for always keeping the +12 V rectifier diode forward-biased, which significantly improves voltage regulation, especially under no-load or light-load conditions.

By looking at the MP2332H’s datasheet, the feedback resistors, inductance, and input/output capacitors can obtain an approximately 1.2 MHz f_SW. The MPL-AL4020-2R2 inductor is a suitable buck inductor choice since it provides low AC losses at 1 MHz f_SW and some margin for peak current saturation.

Final design

Figure 2 shows the final schematics once the calculations are made for the multi-output flyback converter design.

Figure 2 Here is a view of the complete multi-output flyback converter schematic. Source: Monolithic Power Systems

Figure 3 shows the final solution that considers the schematic above as well as the PCB layout.

Figure 3 The evaluation board is based on the complete multi-output flyback converter. Source: Monolithic Power Systems

Figure 4 shows the regulation results for each output in accordance with the total design that was calculated and presented in this article.

Figure 4 The graph shows regulation results for each output at 230 V_AC. Source: Monolithic Power Systems

A practical approach for multi-output auxiliary supplies

This article presented the practical design of a four-output auxiliary flyback power supply. The design covered the main power-stage parameters, including the input bulk capacitor, transformer turns ratio, magnetizing inductance, current-sense resistor, slope-compensation check, and weighted feedback resistor network.

The architecture combines a regulated +5 V rail, a stacked +12 V rail, a post-regulated +3.3 V rail, and a low-current -12 V auxiliary rail. The stacked +12 V output is referenced to the regulated +5 V rail and included in the feedback loop through the weighted resistor network, allowing the flyback controller to regulate a combination of both outputs and improve cross-regulation.

The additional rails are generated with dedicated post-regulation stages. The MP2332H buck converter generates the +3.3 V output from the +12 V rail, while also helping maintain a minimum load on the stacked output. The MP2015A LDO generates the low-current -12 V rail, providing a simple solution for auxiliary analog circuitry.

Overall, the results validate the proposed architecture as a practical approach for multi-output auxiliary supplies, balancing regulation accuracy, efficiency, cost, and circuit complexity without requiring a dedicated isolated regulator for each output.

Joan Mampel is applications engineer at Monolithic Power Systems (MPS).

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