• Become a member
  • Log In
The Institution of Electronics
  • Home
  • About us
    • Our Objectives
    • Our History
    • Governance of the Institution
  • The Electron Magazine
    • 2024
      • 2024 – Winter
      • 2024 – Spring
      • 2024 – Summer
      • 2024 – Autumn
    • 2025
      • 2025 – Winter
      • 2025 – Spring
      • 2025 – Summer
      • 2025 – Autumn
    • 2026
      • 2026 – Winter
  • Members
    • Membership Grades and Fees
    • Members’ Resources
      • The Electron Newsletter
      • The Archives
  • Education and Projects
    • National Electronics Competition
    • Student Members’ Projects
    • Arkwright Engineering Scholarships
  • News
  • Contact Us
  • Menu Menu
Uncategorised

Single-stage design removes 48-V bus in servers

A DC/DC power delivery board from Navitas Semiconductor enables direct conversion from 800 V to 6 V in a single stage. Showcased at NVIDIA GTC 2026, the design eliminates the conventional 48-V intermediate bus converter stage within compute server trays, simplifying power delivery for NVIDIA AI infrastructure.

Using GaNFast power ICs, the board reaches 96.5% peak efficiency at full load with 1-MHz switching and a power density of 2.1 kW/in³. The primary side integrates sixteen 650-V GaNFast FETs in DFN 8×8 packages with dual-side cooling in a stacked full-bridge topology, while center-tapped outputs use 25-V silicon MOSFETs. High-frequency switching enables smaller passives and planar magnetics, increasing power density.

The Navitas power delivery board is about 20% thinner than a mobile phone. Its ultra-low profile allows close placement to the GPU board, minimizing loop inductance to improve transient response and power distribution efficiency.

For more information, contact a Navitas representative or email info@navitassemi.com. A timeline for availability was not provided at the time of this announcement.

Navitas Semiconductor 

The post Single-stage design removes 48-V bus in servers appeared first on EDN.

19 March 2026
http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 0 0 whdsolutions http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png whdsolutions2026-03-19 15:01:012026-03-19 15:01:01Single-stage design removes 48-V bus in servers

Latest news

  • Record high wafer shipments. Can fabs keep pace?12 August 2026 - 07:51
  • Analog uncertainty-aware design: How it replaces Monte Carlo with certifiable yield intelligence11 August 2026 - 16:31
  • Automotive low side output switch architecture suitable for 8 to 48 volt buses and beyond11 August 2026 - 13:26
  • Inference 2.0: How enterprise AI is reshaping AI system architectures11 August 2026 - 07:19
  • Dissecting third-party camera batteries, part 2: Swelling10 August 2026 - 14:00
  • Component and layout rules for USB-C, PD, and CMTI10 August 2026 - 07:53
  • Bear on a power pole7 August 2026 - 13:46
  • Why software-defined systems require a dynamic data layer7 August 2026 - 10:42
  • Paper-based passives show impact of re-thinking substrate6 August 2026 - 16:22
  • Drone bans harm customers and don’t actually close the door6 August 2026 - 13:20
IOE LOGO 2

Become a member

click here

Become a member

click here

Become a subscriber

click here

Become a sponsor

click here

© Copyright - The Institution of Electronics | Website by WHD Solutions
  • Link to LinkedIn
  • Link to Facebook
  • Link to X
Link to: Cellular hotspots: Multi-option evaluation thoughts Link to: Cellular hotspots: Multi-option evaluation thoughts Cellular hotspots: Multi-option evaluation thoughts Link to: UWB SoCs extend ranging and radar performance Link to: UWB SoCs extend ranging and radar performance UWB SoCs extend ranging and radar performance
Scroll to top Scroll to top Scroll to top