Improve PWM controller-induced ripple in voltage regulators

Simple linear and switching voltage regulators with feedback networks of the type shown in Figure 1 are legion. Their output voltages are the reference voltage at the feedback (FB) pin multiplied by 1 + Rf / Rg. Recommended values of Cf from 100 pF to 10nF increase the amount of feedback at higher frequencies, or at least ensure it is not reduced by stray capacitances at the feedback pin.

Figure 1 The configurations of common regulators and their feedback networks. A linear regulator is shown on the left and a switcher on the right.

Modifying this structure to incorporate PWM control of the output voltage requires some thought, and both Stephen Woodward and I have presented several Design Ideas (DIs) that address this.

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I’ve suggested disconnecting Rg from ground and driving it from a heavily filtered (op-amp-based) PWM signal supplied by a 74xx04-type logic inverter. Although this can result in excellent ripple suppression, it has a disadvantage—the need for an inverter power supply, which does not degrade the accuracy of the regulator’s 1% or better reference voltage.

Stephen has proposed switching the disconnected Rg leg between ground and open with a MOSFET. The beauty of this is that no new reference is needed. Although the output voltage is no longer a linear function of the PWM duty cycle, a simple software-based lookup table renders this a mere inconvenience. (Yup, “we can fix it in software!”)

A general scheme to mitigate PWM controller-induced ripple should be flexible enough to accommodate different regulators, regulator reference voltages, output voltage ranges, and PWM frequencies. In selecting one, here are some possible traps to be aware of:

  • Nulling by adding an out-of-phase version of the ripple signal is at the mercy of component tolerances.
  • Cheap ceramics, such as the ubiquitous X7R, have DC voltage and temperature-sensitive capacitances. If used, the circuit must tolerate these undesirable traits.
  • Schemes which connect capacitors between ground and the feedback pin will reduce loop feedback at higher frequencies. The result could be degradation of line and load transient responses.

Circuit

With this in mind, consider the circuit of Figure 2, capable of operation from 0.8 V to a little more than 5 V.

Note: If the regulator output is capable of operation below the FB voltage, a resistor could be connected between FB and a higher DC supply voltage to enable this. For outputs of 0 V, the current through it would have to equal VFB / Rf. The value of Rf would have to be increased to maintain operation to 5 V. However, this approach requires a reference voltage of suitable quality, and much of the advantage of using a MOSFET is lost.

Figure 2 A specific instance of a PWM-controlled regulator with ripple suppression. Only a linear regulator is shown, but the adaptation for switcher operation entails only the addition of an inductor and a filter capacitor.

The low capacitance MOSFET has a maximum on-resistance of under 2 Ω at a VGS of 2.5 V or more. Cg1 and Cg2 see maximum DC voltages of 0.8 V (up to 1.25 V in some regulators). Their capacitive accuracies are not critical, and at these low voltages, they barely budge when 10-V or higher-rated X7R capacitors are employed.

Cf can see a significant DC voltage, however. Here, you might get away with an X7R, but a 10-nF (voltage-insensitive) C0G is cheap. The value of Cf was chosen to aid in ripple management. If it were not present, the ripple would be larger and proportional to the value of Rf. With a 10-nF Cf, larger values of Rf for higher output voltages would have no effect on the PWM-induced ripple; smaller ones could only reduce it. The largest peak-to-peak ripple occurs at duty cycles from 30 to 40%.

The filtering supplied by the three capacitors produces a sinusoidal ripple waveform of amplitude 5.7 µV peak-to-peak. For a 16-bit ADC with a full scale of 5 V, the peak-to-peak amplitude is less than 1 LSbit.

Flexibility

You might have a requirement for a wider or narrower range of output voltages. Feel free to modify Rf accordingly without a penalty in ripple amplitude.

Ripple amplitude will scale in proportion to the regulator’s reference voltage. The design assumes a regulator whose optimum FB-to-ground resistance is 10 kΩ. If it’s necessary to change this for the regulator of your choice, scale the three Rg resistors by the same factor Z. Because the resistors and three capacitors implement a 3rd order filter, the ripple will scale in accordance with Z-3. To keep the same ripple amplitude, scale the three capacitors by 1/Z. You might want to scale the capacitors’ values for some other reason, even if the resistors are unchanged.

Changing the PWM frequency by a factor F will change the ripple amplitude by a factor of F-3. But too high a frequency could encounter accuracy problems due to the parasitic capacitances and unequal turn-on/turn-off times of the MOSFET.

Some regulators might not tolerate a Cf of a value large enough to aid in ripple suppression. Usually, these will tolerate a resistor Rcf in series with Cf. In such cases, ripple will be increased by a factor K equal to the square root of ( 1 + Rcf · 2π · fPWM · Cf ), and the waveform might no longer be sinusoidal. But increasing Cg1 and Cg2 by the square root of K will compensate to yield approximately the same suppression as offered by the design with Rcf equal to 0. If all else fails, there is always the possibility of adding an Rg4 and a Cg3 to provide another stage of filtering.

Tying it all together

 A flexible approach has been introduced for the suppression of PWM control-induced ripple in linear and switching regulators. Simple rules have been presented for the use and modification of the Figure 2 circuit for operation over different output voltage ranges, PWM frequencies, preferred resistances between ground and the regulator’s feedback pin, and tolerances for moderately large capacitances between the FB pins and the output.

The limitations of capacitors with sensitivities to DC voltages are recognized. These components are used appropriately and judiciously. Dependency on component matching is avoided. Standard feedback network structures are maintained or, at worst, subjected to minor modifications only; specifically, feedback at higher frequencies is not reduced from that recommended by the regulator manufacturer. This maintains the specified line and load transient responses.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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