EDA powerhouses align offerings with Intel’s 18A node

The EDA trio—Cadence, Siemens EDA, and Synopsys—was prominent at the Intel Foundry Direct Connect 2025 while lining up AI-driven analog and digital design flows for Intel’s 18A process node. The offerings also included IPs ranging from SerDes to DDR5 to Universal Chiplet Interconnect Express (UCIe).

Next, these EDA outfits inked advanced packaging partnerships by offering workflows for Intel Foundry’s Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology, which combines the benefits of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at die sizes beyond the reticle limit.

Let’s start with EDA flows.

Cadence has certified its RTL-to-GDS flow for 18A process design kit (PDK), which includes the Cerebrus Intelligent Chip Explorer, Genus Synthesis solution, Innovus Implementation System, Quantus Extraction solution, Quantus Field Solver, Tempus Timing solution, and Pegasus Verification System.

Siemens EDA has certified its Calibre nmPlatform sign-off tool and Solido SPICE and Analog FastSPICE (AFS) software tools for 18A production PDK. Likewise, the qualification of Calibre nmPlatform and Solido Simulation Suite offerings for the Intel 18A-P process node is now underway. These EDA tools are also part of the Intel 14A-E process definition and early runsets already available.

Figure 1 Synopsys unveiled an EDA and IP collaboration roadmap with Intel Foundry at the event.

IP and advanced packaging liaison

Cadence has announced a broad range of IPs for the 18A process node. That includes 112G extended long-reach SerDes, 64G MP PHY for PCIe 6.0, CXL 3.0, and 56G Ethernet, LPDDR5X/5 – 8533 Mbps with multi-standard support, and UCIe 1.0 16G for advanced packaging.

Besides IP offerings, Cadence is partnering with Intel Foundry to develop an advanced packaging workflow to leverage EMIB-T technology. This workflow will streamline the integration of complex multi-chiplet architectures while complying with standards.

Figure 2 Cadence is certifying EDA toolsets and IPs for Intel’s 18A process node.

Meanwhile, Siemens EDA has announced the certification of a reference workflow for EMIB-T technology using through silicon via (TSV) technique. It’s driven by the company’s Innovator3D IC solution, which provides a consolidated cockpit for constructing a digital twin. It also features a unified data model for design planning, prototyping, and predictive analysis of complete package assembly.

Synopsys is also employing its 3DIC Compiler to facilitate a reference workflow that enables efficient EMIB-T designs with early bump and TSV planning and optimization. It also features automated UCIe and HBM routing for high quality of results and fast 3D heterogeneous integration. Here, the 3DIC Compiler facilitates feasibility and partitioning, prototyping and floorplanning, and multiphysics signoff in a single environment.

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