Apple’s question for the developer: Are you up for an AI do-over?

Take two, two years later. That’s the 2026 WWDC in a nutshell, at least for developers. And for consumers? If your Apple Watch is more than a few years old, it’s headed for retirement-and-replacement. Ironically, albeit not atypically, Apple…

Would custom memory ease your SoC design?

Memory customization is not always a top priority when a design team plans a new system-on-chip (SoC) project. But often it should be. This may not be an obvious statement. Granted, SRAM claims a lot of area on most SoCs. The speed and power…

Not smart, but solar: Analyzing another thermo-plus-hygrometer

Connectivity is all well and good…well, sort of, as it invariably comes with a price, literally and/or figuratively. Simple’s sometimes best, all things considered, and ambient-light power’s also nice. When you want to monitor and adjust…

Radiosondes: Disposable guardians of the sky

Fifteen miles above you, a small styrofoam box is shrieking into the void. Its voice is binary—relentlessly transmitting temperature, pressure, and wind speed from the freezing stratosphere. In two hours, it will be gone, torn apart by the…

The RF-ready GaN-on-silicon with lower parasitic losses

A new technology addresses a key performance barrier limiting the use of GaN-on-silicon semiconductors in mainstream RF applications. According to Scott Bibaud, president and CEO of Atomera, this will change the economics of GaN in RF by unlocking…

How to design a digital-controlled PFC, Part 4

Editor’s note: This is a multi-part series on how to design a digital-controlled PFC. Previous entries:  How to design a digital-controlled PFC, Part 1 How to design a digital-controlled PFC, Part 2 How to design a digital-controlled PFC,…

MLPerf and the rise of latency-aware LLM benchmarking

Any discussion of modern AI system performance must include MLCommons and its MLPerf benchmark suite, which has become the industry’s de facto standard for measuring machine learning performance. Since its debut in 2018, MLPerf has provided…

Memory card interfaces keep pace with the internal bus evolution race: Part 1

Clock speeds get faster. Per-cycle (and per-clock edge) address and data dollops get larger. And protocols get more efficient. But here we’re talking about external, not internal, buses. Back in 2023, I devoted two blog posts’ worth of content…

The hidden bottleneck in LLM inference and the impact on MLPerf benchmarking

Recent frontier LLM inference benchmarks have highlighted a recurring pattern. GPU-based systems deliver outstanding throughput when latency is not a concern, but their performance drops sharply once real-time response requirements are imposed. This…

Build 2026: Accumulating evidence of Microsoft’s AI independence

Abundant use of the AI acronym is increasingly evident at various industry events. Strip away the hype layer and look deeper, however, and interesting trends still emerge into view. This is my third straight year covering Microsoft’s developer-focused…

Value DSCs streamline embedded control

Digital signal controllers (DSCs) in Microchip’s dsPIC33CK Value Line provide real-time control for cost-sensitive designs. Starting at $0.51 each, they offer consistent pricing regardless of order size. The 16-bit controllers deliver 100-MHz…

Agilex 9 FPGAs power COTS VPX boards

Altera has partnered with Mercury Systems and VadaTech to expand its Agilex 9 FPGA ecosystem with COTS VPX boards for mission-critical defense platforms. These solutions integrate Agilex 9 medium-band Direct RF FPGAs into VPX architectures,…