Triply simply sequence supply voltages

This circuit design for power supply on/off sequencing uses Schmidt triggers for triple-positive-rail timing purposes.

Recent design ideas have explored the utility of timed power supply ON/OFF sequencing and provided circuit designs to implement it.  Figure 1 shows a simple topology using Schmidt triggers for timing the turn ON and OFF of triple positive supply rails.  Here’s how it works.

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Figure 1 This significantly simple supply sequencing scheme leverages Schmidt triggers.

Switching action begins with SPDT S1 in the OFF position which holds the C1 and C2 timing caps discharged.  The latter holds U1 pin 1 at 15v and therefore its pin 2 and the NFET Q2’s gate at zero, forcing the 5Vout rail OFF.

Meanwhile, C1’s discharged state holds U1’s pins 3 and 5 low so pins 4 and 6 sit high.  The former holds enhancement mode PFET Q1 and the 15Vout rail OFF, while the latter does the same for level shifter Q3, PFET Q4, and the 24Vout rail.

Therefore no power flows to the connected loads.  Yet, at least. Figure 2’s left side graphs the sequence of events initiated by actuating S1.


Figure 2 This plot shows power sequence timing when S1 is flipped ON and later flopped OFF.

C2 connects to ground through R3, quickly charging it to the Schmidt trigger low-going threshold in about R3C2 = 1mS.  This inverts U1 pin 2 to 15v, placing a net forward bias of 15 – 5 =10V on NFET Q2, turning it and the 5Vout rail ON.  Thus they will remain as long as S1 stays ON.

Meanwhile, reset of C1 has been released, allowing it to begin charging through R1 + R3.  The first thing that happens occurs at the end of T1 when U1 pin 3 reaches the ~9V Schmidt threshold.  Since the timeout duration is proportional to C1, any desired interval can be chosen with an appropriate RC product.  U1 pin 4 then snaps low, PFET Q1 turns ON and 15Vout goes active.

Of course C1 continues to charge, so at T2 U1 pin 5 also reaches its triggering threshold.  Then its pin 6 snaps low, turning ON Q3, Q4 and 24Vout.  The ratio R4 = 10 R5/(15 – 0.7) was chosen to apply an adequate and safe ~10V drive to Q4’s gate, independently of 24Vin. The S1 flip ON sequence is now complete.

The right side of Figure 2 shows what happens when S1 subsequently flops OFF. First, C1 is promptly discharged through R3, turning OFF Q1, Q3, Q4 and thereby 15Vout and 24Vout, putting them and whatever they power to sleep.  Meanwhile C2 begins ramping up, taking T3 to get to U1’s threshold.  When it completes the trip, pin 2 goes low, turning Q2 and 5Vout OFF. 

Turnoff sequencing is therefore complete.  Nighty night.

Details of the design include D1 and D2.  Their purpose is to make the sequencer’s response to losing and regaining of the input rail voltage orderly, and to do it regardless of whether S1 is ON or OFF.  If  S1 is OFF, then all output rails remain low and (a safe) nothing occurs when the supply voltages return.  If it’s ON, then a normally timed (and therefore safe) power-up sequence is executed.

Note that the MOSFETs should be chosen for adequate voltage and current handling capacities.  Because Q1 has 15v of gate drive and Q2 and Q4 get 10v, none need be sensitive logic-level types.

Okay.  But what if you also need to sequence a negative supply rail?  Figure 3 shows how.


Figure 3 This power switching circuit works with a negative rail.

When the U1 inverter’s input rises above the Schmidt trigger voltage, its output snaps low, causing the 2N3906  to pass Ic = (+15Vin – 0.6)/15k = 0.96mA.  This develops a 10.6V that’s independent of –Vin across the 11k resistor, saturating the NFET.  If symmetrical polarity rails (e.g. +/-15v) are needed, Figure 3 can be added to Figure 1 to provide the negative side with no other modifications required.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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