The advent of co-packaged optics (CPO) in 2025

Co-packaged optics (CPO)—the silicon photonics technology promising to transform modern data centers and high-performance networks by addressing critical challenges like bandwidth density, energy efficiency, and scalability—is finally entering the commercial arena in 2025.

According to a report published in Economic Daily News, TSMC has successfully integrated CPO with advanced semiconductor packaging technologies, and sample deliveries are expected in early 2025. Next, TSMC is projected to enter mass production in the second half of 2025 with 1.6T optical transmission offerings.

Figure 1 CPO facilitates a shift from electrical to optical transmission to address the interconnect limitations such as signal interference and overheating. Source: TrendForce

The report reveals that TSMC has successfully trialled a key CPO technology—micro ring modulator (MRM)—at its 3-nm process node in close collaboration with Broadcom. That’s a significant leap from electrical to optical signal transmission for computing tasks.

The report also indicates that Nvidia plans to adopt CPO technology, starting with its GB300 chips, which are set for release in the second half of 2025. Moreover, Nvidia plans to incorporate CPO in its subsequent Rubin architecture to address the limitations of NVLink, the company’s in-house high-speed interconnect technology.

What’s CPO

CPO is a crucial technology for artificial intelligence (AI) and high-performance computing (HPC) applications. It enhances a chip’s interconnect bandwidth and energy efficiency by integrating optics and electronics within a single package, which significantly shortens electrical link lengths.

Here, optical links offer multiple advantages over traditional electrical transmission; they lower signal degradation over distance, reduce susceptibility to crosstalk, and offer significantly higher bandwidth. That makes CPO an ideal fit for data-intensive AI and HPC applications.

Furthermore, CPO offers significant power savings compared to traditional pluggable optics, which struggle with power efficiency at higher data rates. The early implementations show 30% to 50% reductions in power consumption, claims an IDTechEx study titled “Co-Packaged Optics (CPO): Evaluating Different Packaging Technologies.”

This integration of optics with silicon—enabled by advancements in chiplet-based technology and 3D-IC packaging—also reduces signal degradation and power loss and pushes data rates to 1.6T and beyond.

Figure 2 Optical interconnect technology has been gaining traction due to the growing need for higher data throughput and improved power efficiency. Source: IDTechEx

Heterogeneous integration, a key ingredient in CPO, enables the fusion of optical engine (OE) with switch ASICs or XPUs on a single package substrate. Here, the optical engine includes both photonic ICs and electronic ICs. The packaging in CPO generally employs two approaches. The first one involves the packaging of optical engine itself and the second one focuses on the system-level integration of the optical engine with ICs like ASICs or XPUs.

A new optical computing era

TSMC’s approach involves integrating CPO modules with advanced packaging technologies such as chip-on-wafer-on-substrate (CoWoS) or small outline integrated circuit (SOIC). It eliminates traditional copper interconnects’ speed limitations and puts TSMC at the forefront of a new optical computing era.

However, challenges such as low yield rates in CPO module production might lead TSMC to outsource some optical-engine packaging orders to other advanced packaging companies. This shows that the complex packaging process encompassing CPO fabric will inevitably require a lot of fine-tuning before commercial realization.

Still, it’s a breakthrough that highlights a tipping point for AI and HPC performance, wrote Jeffrey Cooper in his LinkedIn post. Cooper, a former sourcing lead for ASML, also sees a growing need for cross-discipline expertise in photonics and semiconductor packaging.

Related Content

Optical interconnects draw skepticism, scorn
TSMC crunch heralds good days for advanced packaging
Intel and FMD’s Roadmap for 3D Heterogeneous Integration
Heterogeneous Integration and the Evolution of IC Packaging
CEA-Leti Develops Active Optical Interposers to Connect Chiplets
Road to Commercialization for Optical Chip-to-Chip Interconnects

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