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Take back half improves PWM integral linearity and settling time

PWM is a simple, cool, cheap, cheerful, and (therefore) popular DAC technology. Excellent differential nonlinearity (DNL) and monotonicity are virtually guaranteed by PWM. Also guaranteed are a stable zero and a full-scale accuracy that’s generally limited only by the quality of the voltage reference. However, PWM’s integral nonlinearity (INL) isn’t always terrific, and the necessity for low-pass filtering-out of ripple means its speed isn’t too swift either. These messy topics are covered in…

  1. A common cause of, and a software cure for, PWM INL is discussed here in “Minimizing passive PWM ripple filter output impedance: How low can you go?”
  2. The slow PWM settling times (Ts) that can be problematic, together with a way to reduce them, are addressed here in “Cancel PWM DAC ripple with analog subtraction.”

Figure 1 offers a tricky, totally analog strategy for both. The ploy in play is Take Back Half (TBH). It relies on two differential relationships that effectively subtract (take back) the error terms.

  1. For signal frequencies less than or equal to 1/Ts (including DC) Xc >> R and Z = 2(Xavg – Yavg/2).
  2. For frequencies greater than or equal to Fpwm, Xc << R and Z = Xripple – Yripple.

Figure 1 All Rs and Cs are nominally equal. The circuit relies on two differential relationships that effectively subtract the error terms for the TBH methodology.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Because only one switch drives load R at node Y while two in parallel drive X, INL due to switch loading at Y is exactly twice that at X. Therefore, Z = 2(Xavg – Yavg/2) takes back, cancels the error, and has (theoretically) zero INL.

Xripple = Yripple, so Z = Xripple – Yripple = 0 nulls it out, has likewise (theoretically) zero ripple, and ripple filter RC time constants can be made faster and settling times shorter.

The DC conversion component at Z = -PWM_duty_factor * Vref. Conversion accuracy is precisely unity, independent of resistance and capacitance tolerances. However, they ideally should be accurately equal for best ripple and nonlinearity cancellation.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

  • Minimizing passive PWM ripple filter output impedance: How low can you go?
  • Cancel PWM DAC ripple with analog subtraction
  • Temperature controller has “take-back-half” convergence algorithm
  • 20MHz VFC with take-back-half charge pump
  • Take-Back-Half precision diode charge pump

The post Take back half improves PWM integral linearity and settling time appeared first on EDN.

25 June 2025
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