RISC-V IP expands AI capabilities at the edge
SiFive’s Intelligence Gen 2 RISC-V IP portfolio combines scalar, vector, and matrix compute to accelerate AI workloads. The Gen 2 lineup includes the new X160 and X180, alongside the upgraded X280, X390, and XM series. All products feature enhanced scalar and vector processing, while the XM series adds a highly scalable matrix engine.
With up to four cores, the 32-bit X160 and 64-bit X180 target embedded IoT at the far edge. They deliver high efficiency in a compact footprint, extending AI to automotive, robotics, and industrial automation. Their vector engine boosts AI model performance with minimal power and area overhead.
Intelligence Gen 2 products span a wide range of performance, area, and power options within a single scalable Instruction Set Architecture (ISA). Features include a dual-issue, in-order eight-stage superscalar pipeline, narrow-to-wide vector engines, and the XM series’ scalable matrix engine for diverse AI workloads. The CPUs also support the SiFive Scalar Coprocessor Interface (SSCI) and Vector Coprocessor Interface eXtensions (VCIX) to link external AI accelerators and coprocessors.
All five Intelligence Gen 2 products are now available for licensing, with first silicon expected in Q2 2026.
Intelligence Gen 2 product page
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