Parsing PWM (DAC) performance: Part 1—Mitigating errors

Editor’s Note: This is one of a series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. This first part suggests mitigations and eliminations of common PWM error types.

Recently, there has been a spate of design ideas (DIs) published [1-8] which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, and limitations in accuracy. This is the first in what is intended to be a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations will be implementable independently of the others. This DI addresses common types of PWM errors. Let’s review the kinds that a naked microprocessor (µP) PWM output saddles us with.

Errors

I was surprised to discover that when an output of a popular µP I’ve been using is configured to be a constant logic low or high and is loaded only by a 10 MΩ-input digital multimeter, the voltage levels are in some cases more than 100 mV from supply voltage VDD and ground. (I should note that I have not noticed this problem at the output of a 74HC00 NAND gate that the µP drives, although there are other issues that the use of this gate does not address.) Let’s call this saturation errors. I can guess an explanation for this phenomenon, but for my purposes the reason is irrelevant—the solution I’ll propose eliminates the effects this error might otherwise have.

Wow the engineering world with your unique design: Design Ideas Submission Guide

It’s been noted before that digital logics’ rise and fall times and delays contribute to a loss of accuracy in a PWM signal, let’s call these timing errors. However, it’s the difference between the rise and fall characteristics that matters; the type of error that one adds, the other subtracts. Of course, the errors are not identical. But it’s difficult to imagine that either approaches even 1/2 LSB. For that to occur, the voltage transition from the beginning to end of a single clock cycle would have to look something like a straight line between ground and VDD. And so, we should expect the total error from the rise and fall to be something less than ½ LSB, which I suggest should be tolerable. If further reduction is necessary, rather than incur the cost of measurement of each unit at production time and individually customizing compensation, I’d recommend periodic characterization of a group of samples and implementing a common across-the-board correction to all units.

There is a type of error discussed and addressed by Stephen Woodward [8]. This error results from the fact that the PWM output has different resistances (rlo and rhi) in the logic low and high modes of operation, let’s call this a resistance error. (I am indebted to Mr. Woodward for enlightening me in his DI’s comment section about certain aspects of this problem.) Woodward implements an innovative set of digital calculations to ameliorate these errors by pre-warping the PWM duty cycle in accordance with a measurement of the 50% duty cycle error magnitude, presumably at production time. (Note however that the pre-warping corrections near ground and VDD are reduced to zero, and so cannot compensate for, and if care is not taken could be confused with, saturation errors.)

The errors for all duty cycles and the exact pre-warping calculations necessary are disclosed in Woodward’s DI, but let’s consider the peak error magnitude only, which occurs at that 50% duty cycle. The PWM drives a filter presumed to consist of series resistors and shunt capacitors. At steady state, the capacitors have an average voltage eavg. Let’s assign the resistor connected to the PWM a value of R. Ignoring saturation and timing errors, it is easy to see that:

(VDD – eavg) / (R + rhi) = eavg / (R + rlo).

If rlo and rhi were the same:

eavg = VDD / 2.

Since they are different,

eavg = VDD × (R + rlo) / (R + rlo + R + rhi).

Subtracting ideal from the actual, the error is:

VDD × Δr / (4 × R),

where Δr = rlo – rhi.

Of course, few if any digital logic devices will specify the on-resistance flatness Δr. For my µP at 85°C with a 3 V supply,

rhi = (3V – 2.3V) / 10mA = 70Ω maximum and,

rlo = .6V / 10mA = 60Ω maximum.

If we are to work from these specs, we would have to set Δr to 70Ω, even though this is almost certainly excessive. To keep the error for a b-bit PWM less than ½ LSB, we require that:

R > 2b+1 × Δr / 4.

When b = 12, R must exceed 143kΩ. This presents a challenge, and an even greater one for PWMs with more bits; an op-amp must be interposed between the filter and even a mild DC load with load-induced errors are to be avoided. This incurs the errors of the op-amp’s input offset voltage and the voltage drops across R due to input bias currents.

Of course, there are approaches which avoid filters altogether. Again, the prolific Stephen Woodward offers an innovative and effective solution [3, 8]. However, its accuracy is limited by the dual requirements of matching an analog time constant with a pulse width produced by a digital clock, and by a match between the values of two capacitors. Let’s call those to which this design is subject matching errors.

Amelioration

There is a means of implementing a PWM which precludes saturation and matching errors and mitigates resistance errors. The trick is to configure the µP to control a break-before-make analog switch whose input commutates between ground and a voltage reference of the designer’s choice. Otherwise, the circuit operates as a traditional, simple µP-based PWM requiring a filter. The TS5A63157 is a suitable choice for the switch. Its maximum turn-on and turn-off times with a 3 V supply over temperature for the switched inputs are each 7 ns. This is much less than the 50 ns period of the shortest PWM clock cycle of a typical modern high-speed 20MHz µP. And buoyed by the symmetry of these numbers, we should expect a negligible impact on the already less than ½ LSB µP timing error. The switch has an improved on-resistance flatness of 7 Ω maximum with a 3 V supply over a -40°C to +85°C temperature range and 4 Ω with a 4.5 V supply.

The introduction of an analog switch precludes some errors and mitigates another found in PWM designs that lack such.

The maximum on-resistance flatness has been diminished by a factor of at least 10, reducing the resistance error by the same factor. The requirement for the value of R in the above 12-bit PWM example is now reduced to 14.3 kΩ. The analog switch has no saturation error, and there is no matching error with this approach since there is nothing that requires matching.

Let’s suppose the available power supply is 2.5 V. With that as our full-scale voltage, ½ LSB of a 12-bit PWM is 305 µV. To keep the op-amp-induced error to less than ½ LSB, the input bias current must be less than 305 µV / 14.3 kΩ = 21.3 nA.

For the op-amp, we can use an input/output rail-to-rail OP376 (single), OPA2376 (dual), or an OPA4376 (quad). Their input offset voltage is 25 µV maximum at 25°C, limiting the value from -40°C to 85°C to 90 µV courtesy of the unit’s 1 µV/°C maximum temperature sensitivity. The input bias current is 0.2 pA typical and 10 pA maximum at 25°C, but there is no relevant spec for temperature sensitivity. However, the datasheet’s graph of typical current shows about 50 pA at 100°C. Applying the ratio of 50/0.2 to 10 pA yields 2.5 nA. There seems to be a good deal of margin available here, but Texas Instruments should be consulted for more information.

Future work

It’s a valid concern that no “rail-to-rail’ op-amp output swing can encompass its supply rail voltages. The next DI in this series will address this matter. Following that will be a discussion of PWM filters. After that, I’ll discuss a purely software means of reducing the PWM period while maintaining the same number of bits of resolution, placing less of a burden on the analog filters.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

References/Related Content

Double up on and ease the filtering requirements for PWMs
Optimizing a simple analog filter for any PWM
Fast-settling synchronous-PWM-DAC filter has almost no ripple
Cancel PWM DAC ripple and power supply noise
Cancel PWM DAC ripple with analog subtraction
Cancel PWM DAC ripple with analog subtraction—revisited
Cancel PWM DAC ripple with analog subtraction but no inverter
Fast PWM DAC has no ripple

The post Parsing PWM (DAC) performance: Part 1—Mitigating errors appeared first on EDN.