Memory lane: Where SOT-MRAM technology stands in 2024

Spin-orbit transfer magnetic random-access memory (SOT-MRAM) is becoming more visible in next-generation memory offerings for its faster write speeds and much longer endurance. Two recent announcements from prominent semiconductor industry players highlight this new memory technology’s cost and complexity challenges and how they are being addressed to facilitate SOT-MRAM’s mass deployment.

That includes material engineering efforts to further reduce the switching energy per bit and work on optimizing bit cell configuration to shrink the cell area further compared to SRAM. But before we delve into these design initiatives’ technical nitty and gritty, it’s important to understand the fundamentals of SOT-MRAM technology and how it differs from spin-transfer torque magnetic random-access memory (STT-MRAM).

Below are some basic facts about SOT-MRAM and competing STT-MRAM technology and how these non-volatile MRAMs aim to substitute SRAMs in chip designs.

Why SOT-MRAM?

In an era of new non-volatile memory (NVM) technologies, MRAMs have stimulated considerable research interest due to their high area density and low leakage power with comparable speed. However, the operational speed of MRAM is relatively lower than the SRAMs. That has led to the assimilation of advanced switching mechanisms like spin-transfer torque (STT) and spin-orbit torque (SOT) into MRAM designs.

At the cell level, STT-MRAM takes 50% less area with a 74% reduction in leakage power dissipation compared to SOT-MRAM. However, SOT-MRAMs are 4x faster than the STT-MRAM. Moreover, at the architectural level, SOT-MRAM outperforms STT-MRAM in terms of read/ write energy and latency at the cost of marginal chip area and leakage power.

That’s why SOT-MRAM is seen as a promising candidate for replacing SRAM as a last-level cache (LLC) memory in high-performance computing (HPC) applications. Like SRAMs, SOT-MRAM offers a high switching speed in the sub-ns regime and promises robust endurance.

Additionally, being non-volatile, SOT-MRAM bit cells achieve lower standby power than SRAMs at high cell density. Next, SOT-MRAM bit cells can potentially be made much smaller than SRAM cells, translating into a higher bit packing density.

Compared to SRAMs, SOT-MRAMs are a superior candidate because they feature switching of free magnetic layer by injecting an in-plane current in an adjacent SOT layer. On the other hand, in STT-MRAMs, the current is injected perpendicularly into the magnetic tunnel junction (MTJ), and the read-and-write operation is performed through the same path.

Figure 1 In SOT-MRAM, the write current passes parallel to, or across, the layers, so the current can be set arbitrarily high without worrying about wear-out. Source: ITRI

Showcased at the International Electron Devices Meeting (IEDM) held in December 2023, two SOT-MRAM design undertakings can be seen as critical steps toward employing SOT-MRAM for cache memory applications.

Two SOT-MRAM initiatives

First, imec showcased extremely scaled SOT-MRAM devices that can achieve a switching energy below 100 femto-Joule per bit and >1015 endurance. “It’s a reduction of 63% compared to conventional designs, and that helps address a remaining challenge of SOT-MRAM, which traditionally requires a high current for the write operation,” said Sebastien Couet, program director for magnetics at imec.

Scaling SOT-MRAM devices to their extreme—with the SOT track and MTJ pillar having comparable dimensions—also improves the memory’s endurance because it reduces Joule heating inside the SOT layer. “With an endurance beyond 1,015 program/erase cycles, we have experimentally validated our assumption that SOT-MRAM cells can have unlimited endurance, an important requirement for cache memories,” Couet added.

Figure 2 The cross-sectional view of extremely scaled SOT device shows that the SOT track has the same length as the MTG cell, unlike conventional SOT-MRAM designs. Source: imec

Imec has been experimenting with the scaling potential and limitations of single perpendicular SOT-MRAM devices processed on 300-mm wafers. With its findings unveiled at the IEDM 2023, imec has demonstrated that scaling the SOT track not only reduces the footprint of the SOT-MRAM cell, but also largely improves the cell’s performance and reliability.

Also, at the IEDM 2023, Taiwan’s Industrial Technology Research Institute (ITRI) and TSMC provided details about their joint design undertaking on SOT-MRAM in a paper. They claimed that their SOT-MRAM array chip boasts a power consumption of merely 1% of an STT-MRAM device.

“We have further co-developed a SOT-MRAM unit cell that achieves simultaneous low power consumption and high-speed operation, reaching speeds as rapid as 10 ns,” said Dr. Shih-Chieh Chang, director general of Electronic and Optoelectronic System Research Laboratories at ITRI. “Its overall computing performance can be further enhanced when integrated with computing in memory circuit design.”

SOT-MRAM in 2024

It’s important to note that STT-MRAM technology has made some headway in the commercial arena. These memory devices feature SRAM-like performance with low latency and an extended temperature range to cater to diverse environmental demands. That makes them suitable for low-power applications in industrial and Internet of Things (IoT) designs.

However, SOT-MRAM seems to offer more promise for large LLC memory devices in artificial intelligence (AI) and other HPC applications. That makes it an important embedded memory technology to watch in 2024 and beyond.

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The post Memory lane: Where SOT-MRAM technology stands in 2024 appeared first on EDN.

Memory lane: Where SOT-MRAM technology stands in 2024

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