Foundry PDK aims to train engineers on 2-nm process node
A new process design kit (PDK) from imec aims to provide broad access to a 2-nm gate-all-around (GAA) process node and associated backside connectivity for design pathfinding, system research, and training. This foundry PDK features the necessary infrastructure for digital design based on a set of digital standard cell libraries and SRAM IP macros.
The design PDK—enabling virtual digital designs in imec’s N2 chip manufacturing process technology—comes embedded with EDA tool suites from Cadence Design Systems and Synopsys. And it aims to train the semiconductor experts of tomorrow and enable the industry to transition to next-generation process technologies through meaningful design pathfinding.
Source: imec
Foundry PDKs—which provide chip designers access to a library of tested and proven components—are usually available once process technology reaches a critical level of manufacturability. And here comes the catch: there is restricted access and the need for non-disclosure agreements (NDAs). That, in turn, creates a high threshold for academia and industry to access advanced technology nodes like 2-nm during their development.
What imec’s N2 PDK is trying to do is provide young semiconductor engineers in academia and industry with early access to the infrastructure needed to develop design skills on advanced technology nodes such as 2 nm. “The design pathfinding PDK will help companies to transition their designs to future technology nodes and pre-empt scaling bottlenecks for their products,” said Julien Ryckaert, VP of Logic Technologies.
Next, the accompanying training courses will acquaint engineers with the most recent technology disruptions such as nanosheet devices and wafer backside technology. The training program, starting in the second quarter of 2014, will teach subscribers the specificities of the N2 technology node while offering hands-on training on digital design platforms using the Cadence and Synopsys EDA software.
Yoon Kim, VP of Cadence Academic Network, acknowledged that imec’s design pathfinding PDK represents a major milestone for training the next generation of silicon designers. “Imec used Cadence’s AI-driven digital and custom/analog full flows to create and validate the design pathfinding PDK.”
Likewise, Brandon Wang, VP of technical strategy & strategic partnerships at Synopsys, quoted pathfinding PDK as an example of how industry partnerships can broaden access to advanced process technology for the current and next generation of designers. “Our collaboration with imec to deliver a certified, AI-driven EDA digital design flow for its N2 PDK enables design teams to prototype and accelerate the transition to next-generation technologies using a virtual PDK-based design environment.”
According to imec, the design pathfinding PDK platform will extend to more advanced nodes like 1.4 nm.
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