Extending network-on-chip (NoC) technology to chiplets

A monolithic integrated circuit (IC) is one in which everything is implemented on a single silicon die, also called a chip. The maximum practical size for a die using extreme ultraviolet (EUV) lithographic process is around 25 mm x 25 mm = 625 mm2. Although it’s possible to build larger dice, their yields start to fall off rapidly. So, one solution for today’s multi-billion transistor devices is to disaggregate the design into multiple smaller dice mounted on a silicon interposer, presented in a single package. In this case, the smaller dice are referred to as chiplets or tiles, while the final device is known as a multi-die system.

There are multiple advantages associated with adopting a chiplet-based approach. These include increased yield, reduced die cost, and the ability to implement different functions on optimal process technologies. Also, there are increased flexibility and customization options because designers can pick and choose the appropriate chiplets for different applications. This method delivers increased scalability because more chiplets can address higher workload demands and reduced time to market by reusing existing chiplets in various combinations across different products.

A few companies, like Intel, have been using chiplet-based technologies for several years, but these companies are typically outliers who have total control over the entire design flow. The dream is for multi-die system developers to be able to acquire hard chiplet IP from multiple vendors in the same way that today’s SoC designers employ soft IP functions from third-party suppliers.

It’s widely assumed that chiplets will power designs of the future, but what do we mean by future? As little as a year ago, industry pundits were predicting a five-to-six-year timeline for widespread adoption. However, several companies have recently emerged from stealth mode with chiplet offerings, indicating that adopting chiplet technologies may come sooner than expected.

As usual, of course, there’s an elephant in the room. Many of tomorrow’s chiplets will surpass the size and complexity of today’s ICs—ASICs, ASSPs and SoCs. Furthermore, the majority of today’s ICs employ some form of network-on-chip (NoC), which may be viewed as an interconnect IP that spans the entire IC. How will these NoC-based chiplets communicate with each other?

D2D interconnect scenarios

It’s possible to identify a variety of chiplet-to-chiplet interconnect scenarios. Such interconnect is usually referred to as die-to-die (D2D) to avoid confusion with chip-to-chip (C2C) interconnect at the printed circuit board (PCB) level. First, consider some non-coherent D2D interconnect possibilities (Figure 1).

Figure 1 Here are three non-coherent interconnect examples. Source: Arteris

The simplest option involves only two chiplets with direct D2D connections, as illustrated in Figure 1a. A more sophisticated example involves a greater number of dice (Figure 1b), still with direct D2D connections and static mapping mode configuration at boot time. In the case of indirect D2D routing involving chiplet hopping (Figure 1c), there are two possibilities: static mapping mode configuration at boot time or dynamic mapping mode configuration at run time. All three examples in Figure 1 assume heterogeneous dice, but multiple homogeneous (identical) dice are also an option.

Next, consider some coherent D2D interconnect examples (Figure 2). In this case, in addition to any on-chiplet memory like processor and accelerator caches, we are also showing possible deployments of external memory (MEM) like DDR, represented by the larger gray rectangles. These memories, which are external to the multi-die system package, will require on-chiplet memory controller IPs, as shown by the smaller gray rectangles.

Figure 2 The above diagram shows three coherent interconnect examples. Source: Arteris

The simplest form of coherent interconnect is heterogeneous and asymmetric, as illustrated in Figure 2a. In this case, there is a clear host chiplet to which the external memory is connected. At the other end of the spectrum, we have a homogeneous and symmetric architecture (Figure 2c). In this case, every chiplet can talk to its own memory and all other chiplets’ memories. Obviously, this quickly becomes complex. Also, the designers need to be extremely careful with respect to any bottlenecks and latencies associated with D2D communications.

Of particular interest to me is that, while I was attending the world’s first automotive-focused chiplet event, which was held in Leuven, Belgium, there was talk of having a special NoC chiplet that provides all the other chiplets with access to a shared memory while also acting as a kind of arbiter (Figure 2b). The idea would be to have this chiplet, shown as Die X in the figure, act as a hub. The other chiplets are competing for access to the central shared memory, and it’s necessary to regulate the cache coherency. This scenario allows designers to build intelligence into the hub.

A deeper D2D interconnect dive

Let’s look a little deeper into the D2D interconnect (Figure 3). We will start with the NoCs employed on the chiplets themselves. Various NoC technologies are available to designers. For example, the Advanced Microcontroller Bus Architecture (AMBA) from Arm embraces the non-coherent Advanced eXtensible Interface (AXI) protocol and the Coherent Hub Interface (CHI) protocol.

Figure 3 The die-to-die (D2D) interconnect example highlights NoC (left). Source: Arteris

Assuming the designer is using a NoC protocol like AXI or CHI—or NoC IP that can generate and receive AXI or CHI traffic—then any outbound traffic will have to be packed into some streaming interface format like CXS. The packed data is then passed to a link layer controller and associated PHY.

The physical layer will be implemented using something like Bunch of Wires (BoW), Universal Chiplet Interconnect Express (UCIe), or Synopsys eXtra Short Reach (XSR). Similarly, inbound traffic will be passed through the associated PHY and link layer and unpacked into AXI or CHI.

Early days, multiple options

It’s important to note that we are still in the early days of this technology, and people are still figuring out the various ways in which everything and everyone might play together. For example, since chiplets may employ IP blocks from various third-party vendors—and since each IP block may employ its own data width, clock frequency and interconnect protocol—it may be that the NoC needs to accommodate multiple standard protocols that have been defined and adopted by the industry, such as OCP, APB, AHB, AXI, CHI, STBus and DTL.

To address this issue, chiplet designers may turn to the non-coherent and coherent interconnect IPs because both of these NoCs support a wide range of protocols.

If chiplet designers choose to use interconnect IP, they may implement the pack/unpack IP themselves and acquire the link layer and PHY IP from a third-party vendor. Alternatively, it may be that the pack/unpack IP is bundled with the link layer and PHY IP. Yet another alternative is that the pack/unpack IP is provided as a module by the NoC vendor.

Irrespective of the nitty-gritty details, it’s becoming obvious that chiplets and multi-die systems are the wave of the future in electronic design due to their myriad of advantages with respect to cost, yield, flexibility, scalability, and customization. Just when we thought things couldn’t get even more exciting… they did!

Frank Schirrmeister, VP solutions and business development at Arteris, leads activities in the automotive, data center, 5G/6G communications, mobile, aerospace and data center industry verticals. Before Arteris, Frank held various senior leadership positions at Cadence Design Systems, Synopsys and Imperas, focusing on product marketing and management, solutions, strategic ecosystem partner initiatives and customer engagement.

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Extending network-on-chip (NoC) technology to chiplets

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