Chiplets diary: JEDEC’s tie-up with OCP bears first fruit

While the Universal Chiplet Interconnect Express (UCIe) standard for die-to-die interconnect is getting a lot of attention, significant work is also being carried out on another design front: electronic part integration in chiplets. JEDEC, which joined hands with the Open Compute Project Foundation (OCP) in late 2022 to standardize chiplet part descriptions by establishing a framework for the transfer of technology captured in an OCP-approved specification, has provided details about the first major outcome of this collaboration.

The two organizations have jointly announced the integration of OCP’s Chiplet Data Extensible Markup Language (CDXML) and JEDEC’s JEP30 PartModel Guidelines. They claim that integrating CDXML into JEP30 will provide chiplet designers with standardized chiplet part descriptions electronically. “The integration of JEDEC JEP30 and OCP CDXML will create a unified platform that revolutionizes chiplet and electronic part integration,” said Michael Durkan, JEDEC Task Group Chair and PartModel Sponsor.

Figure 1 JEDEC and OCP have teamed up to create an open chiplet economy with a low barrier to entry.

In other words, it’ll open the door for automating system-in-package (SiP) design and assembly using chiplets. Here, chiplet descriptions encompass crucial information for SiP builders, including thermal properties, physical and mechanical requirements, behavior specifications, power and signal integrity properties, and testing of in-package and security parameters.

As a result, component manufacturers can create standardized digital part models that design engineers can easily use in a variety of electronic systems. That, in turn, will lead to a new, open chiplet economy with a low barrier to entry.

OCP, founded by Facebook to drive open-source hardware innovation in the data center ecosystem, aims to provide a collaborative platform for data center and telecom operators, colocation providers, and enterprise IT users. It earlier adopted the bunch-of-wires (BOW) chiplet interconnect technology and has launched the Chiplet Design Exchange (CDX), an open-source working group operating in the Open Domain-Specific Architecture (ODSA) sub-project.

Figure 2 Open Domain-Specific Architecture (ODSA) is a sub-project for developing a chiplet-based architecture. Source: OCP

The CDX group comprises experts from diverse fields, including EDA, system design, IC and SiP design, OSAT, IC fabrication, and material supply. It has recently introduced standardized chiplet models designed for the development and validation of 3D IC designs. That includes machine-readable models for electrical and mechanical properties, which are now part of the JEDEC JEP30 PartModels.

JEDEC’s JEP30, part model guidelines for use with EDA tools, aims to establish the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. The standard can define a part in sufficient detail to enable process efficiencies during the part and product lifecycles.

JEDEC is an independent semiconductor engineering trade organization and standardization body that boasts many of the world’s largest chip companies.

The combination of OCP CDXML and JEDEC JEP30 standards to specify chiplet models aims to lay the foundation of a chiplet design kit (CDK). It will also be a significant step toward a unified structure that supports both chiplets and general electronic parts within the overarching purview of JEDEC.

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