Chiplet design basics for engineers

The world is experiencing an insatiable and rapidly growing demand for artificial intelligence (AI) and high-performance computing (HPC) applications. Breakthroughs in machine learning, data analytics, and the need for faster processing across all industries fuel this surge.

Application-specific integrated circuits (ASICs), typically implemented as system-on-chip (SoC) devices, are central to today’s AI and HPC solutions. However, traditional implementation technologies can no longer meet the escalating requirements for computation and data movement in next-generation systems.

From chips to chiplets

Traditionally, SoCs have been implemented as a single, large monolithic silicon die presented in an individual package. However, multiple issues manifest as designers push existing technologies to their limits. As a result, system houses are increasingly adopting chiplet-based solutions. This approach implements the design as a collection of smaller silicon dies, known as chiplets, which are connected and integrated into a single package to form a multi-die system.

For example, Nvidia’s GPU Technology Conference (GTC) has grown into one of the world’s most influential events for AI and accelerated computing. Held annually, GTC brings together a global audience to explore breakthroughs in AI, robotics, data science, healthcare, autonomous vehicles, and the metaverse.

During his GTC 2025 keynote, Nvidia president, co-founder, and CEO Jensen Huang emphasized the need for advanced chiplet designs, stating: “The amount of computation we need as a result of agentic AI, as a result of reasoning, is easily 100 times more than we thought we needed this time last year.”

Despite a wide range of analyst expectations, explosive growth is undisputed; chiplets are becoming the default way to build large AI/HPC dies (Figure 1).

Figure 1 Chiplet market forecast illustrates its explosive growth. Source: Nomura and MarketUS

Figure 1 above represents the center of gravity of several published forecasts. Tools, technologies, and ecosystems are coming together with a 2026-27 inflection point to facilitate designers’ goal of being able to purchase complex chiplet IP on the open market.

These chiplets will adhere to standard die-to-die (D2D) interfaces, allowing them to operate plug-and-play or mix-and-match. This is expected to generate explosive growth in the chiplet market, reaching at least USD 100 billion by 2035, with some forecasts more than doubling this forecast.

Why chiplets?

One increasingly popular approach is to take an existing monolithic die design and disaggregate it into multiple chiplets. A simplistic representation of this is depicted in Figure 2.

Figure 2 Monolithic die (left) is shown vs. multi-die system (right). Source: Arteris

In monolithic implementations, reticle limits impact scalability, and yields fall as the die size increases. It’s also harder to reuse or modify IP blocks quickly, and implementing all the IPs at the same process technology node can be inefficient.

Chiplet-based multi-die systems offer multiple advantages. When the design is disaggregated into various smaller chiplets, yields improve, and it’s easier to scale designs, currently up to 12x of today’s reticle limit. Also, each IP can be implemented at the most appropriate technology node. For example, high-speed logic chiplets may use the 3-nm node, SRAM memory chiplets the 7-nm node, and high-voltage input/output (I/O) interfaces the 28-nm node.

Observe the red bands shown in Figure 2. These represent a network-on-chip (NoC) interface IP. In a multi-die system, each chiplet can have its own NoC. The chiplet-to-chiplet interfaces, known as die-to-die connections, are typically implemented using bridges based on standard interconnect protocols and physical layers such as BoW, PCIe, XSR, and UCIe.

Aggregation, disaggregation, and re-aggregation

As chiplet-based designs gain traction, it’s essential to understand how today’s SoCs are typically assembled. Currently, the predominant method is to gather a collection of soft IPs, represented at the register transfer level (RTL) of abstraction, and aggregate them into a single, monolithic design. Most of these IPs are sourced from trusted third-party vendors, with the SoC design team creating one or two IPs that will differentiate the device from competitive offerings.

To successfully integrate these IPs into a cohesive design, two other aspects are essential beyond the internal logic that accounts for most of an IP block’s transistors. The first is connectivity information, including port definitions, data widths, operating frequencies, and supported interface protocols. The second is the configuration and status registers (CSRs) set, which must be placed appropriately within the overall SoC memory map to ensure correct system behavior.

Because of this complexity, performing this aggregation by hand is no longer possible. IP-XACT is an IEEE standard (IEEE 1685) that defines an XML-based format for describing and packaging IPs. To facilitate automated aggregation, each IP has an associated IP-XACT model.

As SoC complexity continues to rise, it is becoming increasingly common to take an existing monolithic die design and disaggregate it into multiple chiplets. To support this chiplet-based design, the tools must be able to disaggregate an SoC design into multiple chiplets, each of which may contain many original soft IPs. In addition to partitioning the logic, the tools must generate IP-XACT representations for each chiplet, including connectivity and registers.

Technology Is here now

AI and HPC workloads are advancing quickly, driving a fundamental shift toward chiplet-based architectures. These designs provide a practical solution to meet the increasing demands for scalability and efficient data movement. They require new methodologies and supporting technology to manage multi-die systems’ design, assembly, and integration.

Take, for instance, Arteris’ multi-die solution, which automates key aspects of multi-die design. Magillem Connectivity and Magillem Registers support the assembly and configuration of systems built from IP blocks or chiplets. These tools manage both disaggregation of monolithic designs and re-aggregation into multi-die systems across the design flow.

On the interconnect side, Arteris supplies both coherent and non-coherent NoC IP. Ncore enables cache-coherent communication across chiplets, presenting a unified memory system to software. FlexNoC and FlexGen provide non-coherent options that are compatible with monolithic and multi-die implementations.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm

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