Vcc delay
It was with humble spirit and a good dose of Mea Culpa that a semiconductor company, from whom some very large-scale digital large-scale integration (LSI) chips were purchased, had a problem (later corrected, thank goodness) in that their chips…
GaN fundamentals: Hybrid structures, HEMT, and substrate choices
Part 1 of this article series on gallium nitride (GaN) fundamentals described crystal structures and the formation of the two-dimensional electron gas (2DEG), along with material figures of merit and the transition from depletion-mode to enhancement-mode…
Buck ICs improve AI data center power
Infineon’s XDPE1E multiphase PWM buck controllers and TDA49720/12/06 PMBus POL buck regulators streamline voltage regulation in AI data centers, helping customers boost compute performance per rack. With digital control and telemetry-enabled…
Double-side cooled MOSFETs reduce server heat
AOS has introduced two MOSFETs—the 25‑V AONC40212 and 80‑V AONC68816—in 3.3×3.3‑mm source-down DFN packages with double-side cooling. This packaging supports high power density in DC/DC intermediate bus converters and meets the strict…
224G ICs optimize signal integrity in linear optics
Semtech’s 224-Gbps/lane TIAs and drivers power 800G–3.2T transceivers and optical engines for AI/ML clusters, hyperscale data centers, and cloud infrastructure. Compliant with CEI‑224G‑Linear and LPO‑MSA, they support half-retimed…
UWB SoCs extend ranging and radar performance
The ST64UWB family of ultra-wideband SoCs from ST provides increased range and processing capability for automotive applications. Backward compatible with IEEE 802.15.4z, the chips also support the emerging IEEE 802.15.4ab UWB standard, enabling…
Single-stage design removes 48-V bus in servers
A DC/DC power delivery board from Navitas Semiconductor enables direct conversion from 800 V to 6 V in a single stage. Showcased at NVIDIA GTC 2026, the design eliminates the conventional 48-V intermediate bus converter stage within compute…
Cellular hotspots: Multi-option evaluation thoughts
A cellular data service upgrade prompts new (to this engineer, at least) hardware acquisitions: three models’ worth, four total devices. Smart or superfluous? Read on and decide for yourselves.
When our power went down on December 17, our…
Scoping out the chiplet-based design flow
Today, the design of most monolithic SoCs follows a familiar pattern. Requirements definition leads to an architectural design. Then, the design team selects and qualifies the necessary IP blocks, assembles them into the architecture, and floorplans…
Improve 555 frequency linearity
After more than fifty years of continuous production in bipolar and fully half that in CMOS, there’s really neither room nor reason to question the value and versatility of the venerable 555 analog timer. But if it has any significant limitation,…
Chiplet innovation isn’t waiting for perfect standards
Across markets such as AI, high-performance computing (HPC), and automotive, the demand for computational power continues to accelerate. This demand spans everything from compact edge devices to massive data center servers. Traditionally, that…
Newer, shinier DMM RTDs—part 2
In the first part of this Design Idea, we saw how a cheap op-amp can give remarkably precise readings from an RTD. We also found that it was a false economy, owing to incurable thermal drift. This concluding part fixes that problem by using…
