Cadence debuts LPDDR6 IP for high-bandwidth AI
Cadence taped out an LPDDR6/5X memory IP system running at 14.4 Gbps—up to 50% faster than previous-generation LPDDR DRAM. The complete PHY and controller system optimizes power, performance, and area, while supporting both LPDDR6 and LPDDR5X protocols. Cadence expects the IP to help AI infrastructure meet the memory bandwidth and capacity demands of large language models (LLMs), agentic AI, and other compute-heavy workloads.
The memory system features a scalable, adaptable architecture that draws on Cadence’s DDR5 (12.8 Gbps), LPDDR5X (10.7 Gbps), and GDDR7 (36 Gbps) IP lines. As the first offering in the LPDDR6 IP portfolio, it supports native integration into monolithic SoCs and enables heterogeneous chiplet integration through the Cadence chiplet framework for multi-die system designs.
Customizable for various package and system topologies, the LPDDR6/5X PHY is offered as a drop-in hardened macro. The LPDDR6/5X controller, provided as a soft RTL macro, includes a full set of industry-standard and advanced memory interface features, such as support for the Arm AMBA AXI bus.
The LPDDR6/5X memory IP system is now available customer engagements.
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