Antilog PWM and 2-way current mirror make buffered triangle and square waves

It can be fun (and productive!) to transplant a previous Design Idea into a new context, and even more so when modifying and mixing multiple ideas. Here we’ll combine and comingle the following:

This gets the buffered triangle and square-wave output oscillator shown in Figure 1. It’s linear-in-log tunable from 10 Hz to 1 MHz and controlled with 8-bit PWM.

Figure 1 Incoming 8-bit antilog PWM interface (U1, U2, A1, Q1) generates 80 nA to 8 mA current to control 10 Hz to 1 MHz oscillator (Q2, Q3, Q4, A2, A3). The asterisked parts are precision (metal film) resistors and (C0G) capacitors.

Wow the engineering world with your unique design: Design Ideas Submission Guide

We’ll now proceed to vivisect it.

A single MCU 500 kHz (2 μs per count) PWM output bit controls the anti-log current source. It’s isolated in blue in Figure 2 and works as explained in reference 1 above.

Figure 2 The U1 U2 switching circuit periodically charges precision timing cap Ct to 1.24 V, then exponentially discharges it at (Rt + R1)Ct = 43.4 μs time-constant, storing the result on sample and hold Csh.

The final sample-and-hold antilog Csh voltage = 1.24v*exp(-Tpwm/43.4μs) = 1.184 V to 11.8 μV as Tpwm goes from 2 to 500 μs = 1 to 250 lsb for a Q1 five-decade collector current range of Vcsh/R4 = 8 mA to 80 nA. R1 provides for time constant fine-tuning.

Steering and periodic inversion/reflection of the 80nA to 8mA Q1 collector current into integrator A2 is the job of the Q2, Q3, and Q4 two-way current mirror. It’s covered in reference 2 and in blue in Figure 3.

Figure 3 A two-way current mirror Q2, Q3 ramps A2 C1 integrator up/down at dV/dts ranging from 8E1 to 8E6 volts per second (V/s). Q4 reduces the loading of A3 at high current/frequency while acting as the reference 2 D1.

Comparator A3 switches current mirror polarity when A2’s output reaches the 0.5 V and 4.5 V limits, which are similar to the theory of operation of reference 3, and are determined here by the resistor networks shown below in Figure 4.

Figure 4 R5 R6 set comparator’s 0.5V/4.5V switching points and thus the triangle wave’s 4 Vpp amplitude.

The output frequency versus the PWM setting-controlled current sink is shown in Figure 5.

Figure 5 Frequency versus PWM setting: linear (black) vs log (red).

And that’s the name of that (antilogarithmic) tun(ing).

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.

Antilog PWM and 2-way current mirror make buffered triangle and square waves

Become a member

Become a subscriber

Become a sponsor