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FPGA integrates hard RISC-V cores

Enabling high compute performance at the edge, the Titanium Ti375 FPGA from Efinix packs a quad-core hardened RISC-V block and 370,000 logic elements. It employs the company’s high-density, low-power Quantum compute fabric wrapped with an I/O interface.

The 32-bit hardened RISC-V block (RISCV321 with M, A, C, F, and D extensions and six pipeline stages) offers a Linux-capable MMU, FPU, and custom instruction capability. Paired with an Efinix Sapphire SoC, the Ti375 FPGA helps designers turn a tiny chip into an accelerated embedded compute system.

The Ti375 is manufactured on a 16-nm process and comes in a fine-pitch BGA package with a choice of 529, 676, 900, or 1156 balls. Its full-duplex serializer/deserializer transceiver operates at data rates from 1.25 Gbps to 16 Gbps and supports multiple protocols, including PCIe 4.0, Ethernet SGMII, and Ethernet 10GBase-KR. The FPGA also features a LPDDR4 DRAM controller and MIPI D-PHY.

Samples of the Titanium Ti375 FPGA are shipping now to early access customers.

Ti375 product page

Efinix

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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The post FPGA integrates hard RISC-V cores appeared first on EDN.

12 April 2024
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