Why package lithography matters in heterogeneous chiplet integration

Digital lithography technology (DLT) is promising chipmakers to combine chips with submicron wiring on glass and other large substrates. And this maskless technology is at the center of a strategic partnership between Applied Materials and Ushio, aiming to accelerate the semiconductor industry’s transition to heterogeneous chiplet integration.

Applied Materials has been introducing materials, technologies, and systems that help chipmakers integrate chiplets into advanced 2.5D and 3D packages using hybrid bonding and through-silicon via (TSV) technologies. These initiatives complement heterogeneous integration (HI), which combines multiple chiplets in an advanced package with higher performance and bandwidth than a monolithic chip.

Figure 1 New materials, technologies, and systems are crucial for enabling heterogeneous integration (HI). Source: SystemPlus Consulting Reports

In other words, HI helps semiconductor companies combine chiplets based on a variety of functions, technology nodes and sizes in advanced packages, enabling the combination to perform as a single product. That’s how it helps address the need for more transistors in applications like high-performance computing (HPC) and artificial intelligence (AI) when the ability to shrink transistors with classic 2D scaling is slowing and becoming more expensive.

“Heterogeneous integration is growing rapidly because it helps chip and systems companies overcome the limits of classic 2D scaling, which no longer delivers simultaneous improvements in performance, power and cost,” said Dr. Sundar Ramamurthy, VP and GM of HI, ICAPS and Epitaxy Semiconductor Products Group at Applied Materials. He also claimed that his company’s HI solutions advance the industry’s newest ways to pack more transistors and wiring in 2.5D and 3D configurations.

Why digital lithography technology

Heterogeneous integration enables continued scaling to facilitate bigger chips while driving larger packages with more functionality. However, advanced packages require substrate innovation, which in turn, calls for new materials (glass) and sizes (panel). At this technological crossroads, while packaging lithography can enable the HI roadmap, current technologies pose significant limitations.

Take optical steppers, where a small field requires stitching, besides issues with topography and warpage. Next, direct write systems aren’t capable of high throughput for high-volume manufacturing and offer low resolution for advanced substrates.

Enter digital lithography technology or DLT, a maskless computational architecture for submicron printing. It enables the transfer of a pattern directly onto a substrate without a photomask and field-size limitations. DLT’s advanced computation infrastructure provides enhanced control over the light that patterns the substrate, which dramatically improves yields by adjusting for substrate distortions and die-placement errors.

Figure 2 Digital lithography technology (DLT) aims to be a key enabler in the HI roadmap. Source: Applied Materials

Dr. Ramamurthy claims that DLT is the first patterning system that directly addresses the needs of advanced substrates. “It’s built on a foundation of multiple innovations that enable high resolution at production throughput.”

DLT, which has demonstrated 2-micron interconnect patterning on glass with a roadmap to submicron, claims to provide the highest resolution at production throughput and overlay performance. Moreover, its modular design makes it capable of patterning all substrate materials and sizes.

With the ability to pattern less than 2-micron line widths, DLT enables the highest area density for chiplet architectures on any substrate, including wafers or large panels made of organic materials or glass. That allows DLT to solve unpredictable substrate warpage issues and achieve overlay accuracy.

Lithography for packaging

It’s worth mentioning that Applied Materials and Ushio have already shipped production configuration systems to multiple semiconductor outfits. They have also demonstrated 2-micron panel manufacturing on glass and other advanced package substrates.

The partnership combines Applied Materials’ strength in large panel processing with Ushio’s expertise in lithography for packaging. Ushio has over 20 years of experience building lithography systems for packaging applications.

In this ‘lithography for packaging’ collaboration pact, Applied Materials, which pioneered the technology behind the DLT system, will be responsible for R&D and the definition of a scalable roadmap toward advanced packaging to 1-micron line widths and beyond. On the other hand, Ushio will accelerate the adoption of DLT by leveraging its manufacturing and customer-facing infrastructure.

Figure 3 Package lithography is vital when companies use larger substrates based on new materials. Source: Applied Materials

DLT and its ability to combine chips with submicron wiring could play an important role in the heterogeneous integration of chiplets into 3D packages. Especially when the industry needs larger package substrates based on new materials such as glass that enable extremely fine-pitch interconnects and superior electrical and mechanical properties.

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The post Why package lithography matters in heterogeneous chiplet integration appeared first on EDN.

Why package lithography matters in heterogeneous chiplet integration

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