LPDDR flash: A memory optimized for automotive systems

Next-generation automotive systems are advancing beyond the limits of currently available technologies. The addition of advanced driver assistance systems (ADAS) and other advanced features requires greater processing power and increased connectivity throughout the vehicle. On top of this, automotive OEMs are expanding the user experience (UX) to introduce innovations that improve convenience, efficiency, and safety for drivers and passengers.

This combination of new and advanced features is straining the capacity of traditional automotive E/E architectures (see Figure 1). To address this need, OEMs are consolidating more functions into fewer systems by taking a domain/zonal architectural approach. And these systems often need substantially more non-volatile memory for code storage than is available as embedded flash integrated into processors.

Figure 1 A domain/zonal architecture approach consolidates many safety-critical functions and must be able to process huge amounts of data in real-time as well as store a significantly larger code image. Source: Infineon

Furthermore, many of these consolidated systems are safety critical, and must eliminate both performance and memory access bottlenecks to meet real-time performance deadlines. Finally, automotive systems need to be able to operate in a wide range of harsh environments, including extreme temperatures.

More code storage for software-defined vehicles

The evolution and consolidation in automotive architectures is driving the industry toward software-defined vehicles. The central car computer will connect to the cloud but also needs to have enough centralized processing to be completely autonomous from the cloud for critical driving operations. From a functional standpoint, car functionality will shift to be more service-oriented and maintain a higher level of safety and security.

Part of the challenge OEMs face is the need for more code storage because all this added functionality and connectivity in turn require more complex software. Software is stored in non-volatile memory so it can be updated in the field. Ideally, when there is enough embedded flash on a processor to hold all the software, the processor executes code directly from this on-chip flash in a process known as execute-in-place (XiP). This provides the best execution performance while maintaining system flexibility.

However, when there is not enough embedded on-chip flash, software must be stored in an external flash. But flash bus latency and limited throughput prevent external flash from accessing the system-on-chip (SoC) to XiP at speed. For this reason, the software is copied from flash to faster DRAM to achieve the necessary performance, an approach known as ‘shadow code’.

But a shadow code approach comes at the cost of additional DRAM memory—plus associated board space—to store the copy of the software. In addition, system start takes longer, which negatively impacts user experience, or worse, operational safety.

For next-generation automotive systems, neither approach is sufficient. Specifically, to meet the real-time requirements of a consolidated domain or zone, a higher performance, highly integrated SoC processor is required. To achieve such a level of integration, these SoCs must utilize smaller manufacturing process nodes.

This enables SoCs to provide all the integrated capabilities with a single chip in a cost-effective manner. However, as manufacturing process nodes shrink to 22 nm and below, it becomes expensive to integrate embedded flash in the densities required. Thus, an alternative to embedded flash for XiP is needed.

Overcoming external memory bottlenecks

To be able to take full advantage of high-performance SoCs built using smaller process nodes, engineers need to once again turn to external NOR flash. Figure 2a shows one approach to using external flash where the SoC can XiP from an embedded flash while an external NOR flash is used as a memory extension.

Figure 2 A traditional execute from embedded flash architecture uses an external NOR flash as a memory expansion to hold software that is loaded into embedded flash for XiP. This approach is limited by embedded flash capacity as well as xSPI throughput (left). A next-generation execute from external flash architecture combines the flexibility of an embedded flash approach with the performance of DRAM (right). Source: Infineon

The problem with the former approach is the limited bandwidth of the xSPI bus used to interface between the embedded flash and external NOR flash. Standard xSPI throughput is 400 MB/s, and even at 16-bits, xSPI at 200 MHz can only achieve 800 MB/s maximum throughput. This falls substantially short of what is required to support real-time code execution.

In addition, xSPI uses a multiplexed command/address/data bus that negatively impacts effective throughput because code reads cannot be pipelined efficiently. Furthermore, LVCMOS leaves little room for advancement beyond 200 MHz.

Figure 2b shows an alternative approach that directly executes code from external flash. This approach eliminates the need for embedded flash by utilizing a high-performance low power double data rate (LPDDR) interface that enables XiP from external flash.

LPDDR: Proven interface finds a new use case

LPDDR is a memory interface commonly used with DRAM for high-performance data access. The LPDDR interface has been adapted to work with NOR flash and optimized for efficient XiP from external NOR flash. With a throughput potential of many gigabytes per second, LPDDR flash provides the performance of DRAM with the non-volatile reliability and flexibility of embedded NOR flash. It’s the best of both worlds.

One of the factors that makes the LPDDR NOR flash interface a compelling technology is that its physical layer is completely compatible with the LPDDR standard interface. This compatibility reduces the risk associated with adopting a new interface as the signal integrity of LPDDR has already been proven in the market in myriad real-world applications and operating environments.

At a high level, the LPDDR NOR flash interface is focused on code storage and real-time XiP for applications where code is written once and read many, many times. Thus, the interface is optimized to increase read performance overwrite efficiency. Again, the physical layer is untouched, so optimizations have been implemented in the controller protocol. These optimizations are tailored to meet the requirements of high-performance applications like autonomous vehicles.

The LPDDR advantage

The benefits of LPDDR NOR flash over SDRAM and xSPI-based NOR flash architectures are substantial. Take the example of the LPDDR4-based SEMPER X1 NOR flash, which is specifically optimized for operation in automotive applications. In comparison to standard NOR flash, it provides the throughput of LPDDR to support XiP using an external NOR flash (Figure 3).

Figure 3 SEMPER X1 has been optimized for operation in automotive applications and to support XiP using an external NOR flash. Source: Infineon

The entire memory architecture has been designed for functional safety and reliability to ensure uninterrupted operation in applications where failure is not an option.

To understand the advantages of LPDDR flash over both xSPI NOR flash and DRAM, consider how the SEMPER X1 utilizes the LPDDR4 interface to improve real-time performance (see Figure 4).

Figure 4 The LPDDR4 interface optimized for data read access provides superior performance compared to LPDDR4 SDRAM and xSPI NOR flash, as illustrated by these performance comparison figures. Source: Infineon

XiP from external memory becomes possible through several different optimizations as shown in Figure 4:

Separating read from write

SEMPER X1 NOR flash has multiple ports: a quad SPI for write/read and an LPDDR4 dedicated for read only. Eliminating write operations from the LPDDR4 port enables the interface to be further optimized than if it also supported write operations.

Faster training

Eliminating the write path in LPDDR eliminates the need for write DQ training. This results in 100x faster training compared to LPDDR4 SDRAM.

Faster read commands

When accessing DRAM, it takes four commands to retrieve data. The LPDDR4 interface of SEMPER X1 uses a simpler format, requiring just two commands (Figure 5). Combined with no banking restrictions, row activation, or refresh compared to LPDDR4 DRAM, SEMPER X1 delivers 5x faster random read transactions. It’s also 5x faster than xSPI NOR flash for a 32-byte single read operation from command request to read data.

Figure 5 LPDDR flash requires just two commands—NVR-1 and NVR-2—to complete each read operation. Source: Infineon

Separate command from data

A typical xSPI interface is 8 pins, and both commands and data must share that bus. LPDDR, in contrast, has separate pins for commands and data, enabling the efficiency of command pipelining. The result is 20x better performance for pipelined random read transactions compared to xSPI NOR flash.

Data bus efficiency

The underlying embedded charge trap (eCT) technology in this memory ensures that there is no need for periodic refresh to interrupt throughput. That enables it to achieve up to 99% bus efficiency at 125° C, a 14% improvement compared to LPDDR4 DRAM.

Better determinism

Determinism is a measure of the consistency of performance. Zone controllers often have many cores operating in parallel to provide the necessary processing capacity required for consolidated automotive systems. When multiple cores share memory, accesses by one core can create delays in accesses by all the other cores. Such delays can impact real-time reliability. A memory with multiple banks allows each core to have its own bank. This minimizes memory access interference and interdependence between cores, thus improving overall determinism and reliability.

Zero downtime updates

With multiple banks, firmware-over-the-air (FOTA) updates can be loaded into an alternate memory bank. Once the update is complete and has been authenticated, the system can switch over to the alternate bank, allowing for a seamless transition to the update with zero system downtime.

Better power efficiency

LPDDR optimizations impact more than just performance and reliability. Compared to xSPI NOR flash, SEMPER X1 consumes 8x lower read energy per MB while providing 8x higher throughput performance. For high-performance applications, these savings add up fast.

Outperforms shadow code

The ability of LPDDR flash to provide throughput of 3.2 GB/s puts its XiP performance on par with SDRAM using a shadow code approach. In addition, the LPDDR approach requires fewer memory ICs, has faster setup time, and consumes less energy, making it a compelling alternative to SDRAM.

Scalability for the future

A key advantage of LPDDR is that it is a scalable interface that can support the increasing complexity of automotive applications in the future. xSPI is limited in its ability to scale as LVCMOS has little room for advancement past 200 MHz, capping bandwidth at 400 MB/s (x8) and 800 MB/s (x16). In short, xSPI can no longer keep up.

LPDDR4, on the other hand, allows for frequencies up to 1,600 MHz and can scale throughput from 1,600 MB/s to 12,800 MB/s (Figure 6). With this wide range of capacity, LPDDR4 offers the scalability and performance required for XiP in increasingly advanced systems, with newer LPDDR generations providing even more headroom.

Figure 6 xSPI is limited in its ability to scale, capping performance at 800 MB/s (x16). In contrast, LPDDR4 allows for frequencies up to 1,600 MHz and can scale from 1,600 MB/s to 12,800 MB/s, providing the scalability and performance required for XiP in today’s and tomorrow’s increasingly complex automotive applications. Source: Infineon

As the computational load and software complexity of vehicles increase with more automation, greater convenience and advanced user experience, greater code storage is required. Many of these software-defined functions are mission-critical and need real-time code execution to maintain reliability and safety.

To maintain performance and efficiency, today’s automotive applications need a fast underlying memory array to leverage all possible efficiencies. However, at advanced manufacturing process nodes, automotive-qualified embedded non-volatile memory technology faces high cost (die area) and lack of scalability. An external memory approach is required but the needs of the increasingly software-defined architecture of vehicles exceed the capabilities of today’s most advanced xSPI NOR flash, which simply cannot provide real-time XiP performance.

LPDDR is a key technology for next-generation automotive systems, providing an interface to external flash memory with enough performance to enable real-time computing and XiP capabilities for domain and zone controllers. With efficiencies such as 20x faster random read transactions and 8x lower read energy consumption per megabyte, LPDDR enables next-generation vehicles to provide advanced capabilities with enhanced safety and architectural flexibility.

Sandeep Krishnegowda is VP of marketing and applications for flash solutions at Infineon Technologies.

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LPDDR flash: A memory optimized for automotive systems

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