FPGA architecture: Radiation particle types and single event upsets (SEUs)

As FPGA manufacturing migrates to smaller geometries, the process change has delivered extraordinary gains in density, speed, and power efficiency. However, these gains have come at a cost in terms of single event upset (SEU) sensitivity.

Starting in the mid-1990s, the FPGA industry began experiencing a more noticeable rate of SEU sensitivity in 2D planar transistor architectures. Smaller process geometries require less capacitance to store a given state, so a lower amount of energy can disrupt the stored state. Sensitivity increased proportionally to the geometry shrink.

Moving to tri-gate 3D FinFET geometries at 22 nm helped reduce SEU sensitivity compared to 2D planar, but as tri-gate geometry reduces, SEU sensitivity will continue to increase. A bit flip used to require a direct, high-energy particle strike; now even lower-energy neutrons, alpha particles from packaging materials, or even secondary particles generated within the device substrate itself can trigger bit flips.

The result is an unavoidable increase in SEU susceptibility in FPGAs as process nodes scale smaller and FPGAs are deployed in more applications. Part 1 of this mini-series examines SEU radiation particles and related SEU challenges for FPGA applications that require robustness and predictability in ground-based and terrestrial applications.

Radiation particle types and SEU

A variety of particle types can interact with an FPGA and negatively impact system functionality. These particles differ in mass, charge, and energy strength, and interact with the semiconductor material through distinct physical mechanisms. The following discussion focuses on four particle types that lead to SEUs in FPGAs: heavy ions, protons, neutrons, and alpha particles.

Heavy ions

Heavy ions, which are caused by galactic cosmic rays and solar flares, are the most potent SEU-inducing particles for space and high-altitude environments. To a lesser degree they can impact ground-based systems. These particles have a heavy nucleus, high linear energy transfer (LET) values, and a positive charge.

When heavy ions traverse through the silicon substrate, they deposit large amounts of charge in their path, generating free electrons and holes that can disrupt a memory cell’s stored charge. A memory cell is constructed with transistors, and if the accumulated charge added by the heavy ion exceeds the minimum charge required by a cell’s transistor, the memory cell state can switch, resulting in a bit flip. In other words, heavy ions cause bit flips through direct ionization.

Figure 1 Heavy ion striking a planar transistor result in ionization along its path, depositing charge and potentially impacting the transistor state. Source: Efinix

Figure 2 Junction current is induced from charge collection and diffusion over time. Source: Efinix

Protons

Protons are a secondary radiation particle caused by cosmic rays and solar flares but are weaker than heavy ions. When cosmic rays hit the earth’s atmosphere, they cause nuclear interactions that produce protons. Proton particles have a lighter nucleus, lower linear energy transfer (LET), and are positively charged.

Although the LET is lower, protons can cause indirect ionization via nuclear reactions with semiconductor material. When protons collide with semiconductor material, they can cause a higher LET secondary ion (known as a recoil ion), which can have enough energy to cause a bit flip.

Protons are abundant in the inner and outer Van Allen radiation belts. The stronger inner belt resides 370 – 620 miles above the earth’s surface. Protons are not considered a significant concern for SEU in ground-based systems.

Figure 3 Proton particle striking silicon substrate shows spallation and generates a recoil ion, which has ionization along its path depositing charge, potentially impacting the transistor state. Source: Efinix

Neutrons

Neutrons are another secondary radiation particle created by cosmic rays. Like protons, neutrons are created when cosmic rays hit the earth’s atmosphere and cause nuclear interaction. Compared to protons, neutrons are slightly heavier, have a higher LET, and are neutral in charge.

Neutrons also collide with semiconductor material causing secondary high LET recoil ions, which carry a strong enough charge to cause an SEU. Neutrons have also a higher penetration value and can pass through common building materials like concrete.

At commercial aviation altitudes, the number of neutrons in the atmosphere is approximately 300 times higher than at sea level. Although ground-based systems are not as exposed, neutron-induced soft error rates are still a growing concern for data centers and industrial systems operating high-density FPGA arrays.

Figure 4 Neutron particle striking silicon substrate shows spallation and generates a recoil ion, which has ionization along its path depositing charge, potentially impacting the transistor state. Source: Efinix

Alpha particles

Alpha particles are a terrestrial particle caused by trace radioactive element decay in silicon packaging materials. Packaging materials contain uranium and thorium in chip packaging and solder bumps. When the trace radioactive element decays, it produces helium nuclei alpha particles.

Alpha particles have a light nucleus, high LET compared to neutrons and protons, and are positively charged. They have a very low penetration value. However, because the packaging materials are very close to the silicon substrate and because of their higher LET, alpha particles can cause SEUs in FPGAs.

Alpha particles in packaging were the original source of DRAM soft errors found in 1978. Since then, manufacturing improvements for packaging materials have helped reduce the probability of high LET alpha particles due to radioactive decay.

Figure 5 Alpha particle emitted from radioactive decay in the package and depositing a charge along its path can impact the transistor state. Source: Efinix

SEU challenges in FPGA architectures

An SEU event can impact several resources within the FPGA architecture, including configuration RAM (CRAM), look-up tables (LUTs), routing, registers, and embedded memory (block RAM). However, a bit flip may or may not impact the design’s functionality.

In unused resources, a bit flip will not affect the functionality.
In resources used for non-critical functions (like test circuits, image/video signal processing, or audio data), a bit flip may not impact the design significantly.
A bit flip in mission-critical systems, like flight control, defense systems, medical systems and energy grid systems, can have serious consequences.

The following subsections describe how SEUs impact the most vulnerable FPGA resources: CRAM, routing, LUTs, registers, embedded memories, and the broader design functionality that depends on their correct operation.

Configuration RAM (CRAM)

From an architecture perspective, SEUs in FPGA CRAM have the most negative consequences. Unlike a processor or ASIC, where logic behavior is fixed in silicon, an FPGA’s function, including routing connections, logic functions, and I/O standard settings, is defined by the CRAM contents. When the FPGA powers up, the CRAM is programmed with a specific bitstream for a specific application.

The function is expected to remain constant. The CRAM controls settings related to routing, LUTs, and configuration of hard IP like transceivers and DDR controllers that are now a part of most FPGA architectures. CRAM SEUs are persistent compared to data path storage elements and can go undetected without built-in detection circuits.

Routing

FPGA routing connects logic, embedded memory, set/resets, and I/O to and from the programmable fabric. A high percentage of the CRAM is dedicated to routing.

A flipped routing bit could lead to a disconnect on a signal path, set/reset path, or clocking path where clock trees are more flexible via configuration of the FPGA. In addition to disconnects, a routing upset could unintentionally merge two independent signal nets, resulting in driver contention, illegal voltage logic levels, and logic corruption.

LUTs

LUTs are an FPGA’s fundamental logic primitive, each implementing an arbitrary Boolean function of four to six inputs. The truth table values are stored in CRAM. Compared to routing, a lower percentage of the CRAM is dedicated to programming the LUTs.

An SEU in CRAM that impacts an LUT alters the truth table and can result in unanticipated results for a specific input state. For example, in a 4-input LUT, inputs of 1010 may be configured to output a 1. An LUT bit flip at address 1010 results in an output of 0, which could be a similar result for another combination of inputs, resulting in a missed condition or trigger, or incorrect control state calculation.

An unexpected bit flip can result in logic that enables an external I/O tri-state, or changes a voltage setting, drive strength, or termination, resulting in external I/O conflicts, poor signal integrity, and potential damage to other board components.

Registers

Registers are fundamental elements within FPGA architecture. They can be used as up/down counters, store control states, store status, and pipeline or buffer data. Registers do not have a persistent state if they are clocked and are not loaded from CRAM. Therefore, a register bit flip can be benign if it’s buffering non-critical data.

The corrupted data may make its way downstream and have no consequences. Incoming correct data to the register is then loaded on the next clock cycle. However, a bit flip in a state machine could put the state machine into an unknown state, freezing the design’s functionality or triggering an unintended action. A status register bit flip could trigger a similarly unwanted action.

Embedded memory (block RAM)

Block RAM is like a register in terms of SEU impact. A bit flip may not persist, depending on the functionality (look-up table, data buffering, or soft processor memory). Block RAM is not loaded from CRAM but can be initialized when you program the FPGA with a bitstream. If not initialized, the block RAM contents are 0 after the FPGA enters user mode.

Block RAM stores values that the design actively reads, writes, and depends upon during normal operation. The consequences of a bit flip depend on the block RAM use. For example, a bit flip can propagate downstream in video, image, or audio buffering applications without harm.

However, a bit flip within a stored soft processor program may have consequences like a control register where the executing software may branch to an unexpected area of code. A bit flip in block RAM that stores DSP coefficients can lead to a computational error that manifests itself as inaccurate results for an AI LLM or persistent unwanted noise in a filter.

SEU impact on FPGA functionality

The cumulative effect of uncorrected SEUs across CRAM, routing, LUTs, registers, and block RAM is a gradual and silent degradation of the design’s integrity. A single SEU could lead to a hard failure immediately but usually it will be unambiguous. Accumulated SEU failures follow a probabilistic profile.

The first upset may be functionally insignificant, the second may alter behavior in a rarely exercised path, and the third may corrupt a critical state register in a way that cascades into a system-level failure. This accumulation without detection or a means to correct it can result in increasing failure probability over time.

Mik Ichiba is principal field applications engineer at Efinix. He is a seasoned semiconductor and embedded systems professional with more than 30 years of experience spanning hardware architecture, PCB design, ASIC development, FPGA architecture, and system-level engineering. Throughout his career, Mik has worked across the hardware design lifecycle, helping organizations translate complex technical requirements into practical, high-performance solutions.

Editor’s Note

This is Part 1 of the mini-series about SEU challenges in FPGA architectures. Part 2 will cover SEU detection, recovery, and validation for FPGA applications that require robustness and predictability in ground-based and terrestrial applications.

FPGA architecture: Radiation particle types and single event upsets (SEUs)

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