The ASIC design remake in the AI era

The traditional ASIC design model—focusing on relatively stable standards and well-defined functions—is now under pressure. That’s partly because AI workloads are highly diverse, compute-intensive, and tightly coupled to software behavior and system context. Consequently, ASICs, besides being application-specific, are now increasingly becoming system-specific.

Take the case of a custom chip for LLM inference, where the prefill and decode stages are now running on separate chips. So, there are two ASICs instead of one: the compute-intensive part of the application (prefill) and the memory-bandwidth-limited part of the application (decode). That shows how ASICs are increasingly becoming modular and disaggregated with cross-domain collaboration spanning architecture, packaging, and manufacturing.

Read the full article at EDN’s sister publication, EE Times.

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