• Become a member
  • Log In
The Institution of Electronics
  • Home
  • About us
    • Our Objectives
    • Our History
    • Governance of the Institution
  • The Electron Magazine
    • 2024
      • 2024 – Winter
      • 2024 – Spring
      • 2024 – Summer
      • 2024 – Autumn
    • 2025
      • 2025 – Winter
      • 2025 – Spring
      • 2025 – Summer
      • 2025 – Autumn
    • 2026
      • 2026 – Winter
      • 2026 – Spring
  • Members
    • Membership Grades and Fees
    • Members’ Resources
      • The Electron Newsletter
      • The Archives
  • Education and Projects
    • National Electronics Competition
    • Student Members’ Projects
    • Arkwright Engineering Scholarships
  • News
  • Contact Us
  • Menu Menu
Uncategorised

Software accelerates 3D interconnect design

The Keysight Chiplet 3D Interconnect Designer automates the design of 3D interconnects for chiplet and 3DIC advanced packages. By removing time-consuming manual steps, the tool streamlines the optimization of complex interconnect structures—including vias, transmission lines, solder balls, and micro-bumps—while ensuring signal and power integrity in densely packed systems.

Part of Keysight’s EDA portfolio, the software provides a pre-layout workflow for advanced multi-die integration, UCIe compliance, automated routing, and robust simulation capabilities. It handles complex geometries—including hatched or waffled ground planes—that are critical for addressing manufacturing and fabrication constraints, particularly in silicon interposers and bridges.

The software can operate independently or alongside Keysight’s other EDA tools, enabling teams to seamlessly incorporate 3D interconnect workflows into their existing design environments.

To learn more about the Keysight Chiplet 3D Interconnect Designer (W3510E) and request a quote, visit the product page linked below.

W3510E product page 

Keysight Technologies 

The post Software accelerates 3D interconnect design appeared first on EDN.

19 February 2026
http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 0 0 whdsolutions http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png whdsolutions2026-02-19 17:09:182026-02-19 17:09:18Software accelerates 3D interconnect design

Latest news

  • Secrets of Oscilloscope Time Measurements14 August 2026 - 13:44
  • Radon: Level detection, risk determination, and as-needed mitigation13 August 2026 - 13:16
  • TI a first mover in CAN XL transceivers13 August 2026 - 10:13
  • Four-channel USB-UART IC boosts server management13 August 2026 - 05:08
  • eFuse speeds overcurrent detection13 August 2026 - 05:08
  • Memory platform tackles AI bottlenecks13 August 2026 - 05:08
  • 6.5-kV SiC MOSFET reaches 8-kV blocking13 August 2026 - 05:08
  • Made by Google 2026: This limited silicon-supply situation really sucks13 August 2026 - 05:08
  • Cheap and cheerful LMC555 RC PWM pulse generator12 August 2026 - 13:56
  • Record high wafer shipments. Can fabs keep pace?12 August 2026 - 07:51
IOE LOGO 2

Become a member

click here

Become a member

click here

Become a subscriber

click here

Become a sponsor

click here

© Copyright - The Institution of Electronics | Website by WHD Solutions
  • Link to LinkedIn
  • Link to Facebook
  • Link to X
Link to: Samsung leads with HBM4 DRAM performance Link to: Samsung leads with HBM4 DRAM performance Samsung leads with HBM4 DRAM performance Link to: Navitas tightens SiC losses with refined TAP Link to: Navitas tightens SiC losses with refined TAP Navitas tightens SiC losses with refined TAP
Scroll to top Scroll to top Scroll to top