Stress analysis
Sometimes, getting true stress levels can be tricky because things happen that are sneaky.
Stress analysis is often required to confirm that a designed product will perform properly in hazardous environments. Rather than trying to ascertain a “mean time between failures” (MTBF) or a “mean time to repair” (MTTR), the required assumption can also be that failure is simply unacceptable, no matter what, with the further assumption that repairs will simply not take place. For example, when spacecraft are sent out, they usually had better just work…period.
Among the tools that can be brought to bear toward that end, we have MIL-STD-975M (NASA), in which derating guidelines are given for all kinds of electronic parts. If your components all operate within stress limits as defined in that document, it will be assumed that your product will function as required after having been launched.
Sometimes though, getting true stress levels can be a bit tricky because sneaky things can happen, as in the following case study. It exemplifies the following lesson: when doing a stress analysis on the components that have been incorporated into a product, don’t overlook the possibilities of transient conditions. Your design might not be as safe and secure as you think.
Imagine we have a half-bridge switch mode inverter. We can make a very simple SPICE model for it and see what happens when the circuit is first energized.
Figure 1 A simple SPICE model for an also-simple circuit shows what happens when it is first energized.
L1 and R3 are a crude model of the primary winding of a loaded inverter transformer. We look at the voltage excursion that capacitor C1 undergoes when the circuit is first energized and see that the voltage there follows an under-damped wave shape.
Even though the final value of the C1 voltage is headed for half the rail voltage (minus just a little bit of that half to account for switching losses), there is a momentary voltage excursion that goes to a positive peak which is well above that final settling point.
Excerpting from MIL-STD-975M, we find the following.
Figure 2 These excerpts from MIL-STD-975M are relevant to the example half-bridge switch mode inverter circuit.
Taking one particular CLR81, 220 µF capacitor whose nominal voltage rating is 75 volts, if we apply the derating requirement of 0.4, we have an allowable maximum voltage of 75 x 0.4 = 30 volts.
If we are so blithe as to say that C1 will have 14 volts across itself, we will find a stress level of 46.7%, but what we really have is a peak excursion during power-on rising to 21.451 volts, which means a stress level on C1 of 71.5%. We will still be okay, but we will have significantly less of a safety factor to the maximum stress level than we might have originally thought.
Sneaky stuff like this could result in you overlooking an over-stress condition. It is therefore important to consider every circumstance, from stead-state service to any kind of transients to which your designed product’s components may (or maybe more accurately, will?) be subjected.
John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).
Related Content
- Semiconductor Reliability and Quality Assurance–Failure Mode, Mechanism and Analysis (FMMEA)
- Design for reliability: You have the tools
- Electronic Components Derating – Made Easy
- Connector voltage stress, Part 1 and Part 2
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