Stacked-die half-bridge boosts MOSFET power density
Using a vertically stacked-die design, AOS’s DFN6×5 AmpStack package integrates two MOSFETs configured as a high-side/low-side half-bridge. It increases power density and maximizes available PCB space compared to a solution using two discrete DFN5×6 MOSFETs. The package enables high-density power conversion applications ranging from megawatt AI factories to power tools.
The AOPL66801 80-V MOSFET showcases the new half-bridge package with an optimized switch-node clip connecting the high-side and low-side MOSFETs. This architecture minimizes parasitic inductance within the package. Compared to a standard discrete solution, it also reduces PCB parasitic inductance, minimizing phase-node voltage ringing and decreasing stress on the MOSFETs. Key specifications for the AOPL66801 include:
An integrated Kelvin sense pin maintains gate-voltage stability during high di/dt switching. The dedicated connection provides a more effective high-side gate-drive path, helping reduce switching losses. The device also supports a maximum junction temperature of 175 °C for increased thermal capability.
The AOPL66801 is available now in production quantities with a 16-week lead time. Pricing is $6.16 per unit in 1000-piece quantities.
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